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| author | Nao Pross <np@0hm.ch> | 2021-05-22 02:35:19 +0200 |
|---|---|---|
| committer | Nao Pross <np@0hm.ch> | 2021-05-22 02:35:19 +0200 |
| commit | ec4eef5be25505c7673959b708ce9a9b8eaf7f21 (patch) | |
| tree | 9381dbb9115bd4493c810a63d2929cd70a993474 /tex | |
| parent | On RTL design (diff) | |
| download | DigDes-ec4eef5be25505c7673959b708ce9a9b8eaf7f21.tar.gz DigDes-ec4eef5be25505c7673959b708ce9a9b8eaf7f21.zip | |
Update TODO
Diffstat (limited to '')
| -rw-r--r-- | tex/testbench.tex | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tex/testbench.tex b/tex/testbench.tex index 60e654b..d7fe70f 100644 --- a/tex/testbench.tex +++ b/tex/testbench.tex @@ -5,7 +5,9 @@ written by a \emph{test designer}. \subsection{Simulator} VHDL simulates digital systems using \emph{delta cycles}. -%% TODO: notes on how delta cycles work + +%% TODO: notes on how delta cycles work, read +%% https://stackoverflow.com/questions/43652630/delta-cycles-and-waveforms \subsection{Transport delay} To model a time delay of a signal there are two ways: |