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-rw-r--r--DigDes.tex (renamed from Vorlage.tex)30
-rw-r--r--tex/vhdl.tex42
2 files changed, 56 insertions, 16 deletions
diff --git a/Vorlage.tex b/DigDes.tex
index 10180b5..63d58aa 100644
--- a/Vorlage.tex
+++ b/DigDes.tex
@@ -1,6 +1,6 @@
% !TeX program = xelatex
% !TeX encoding = utf8
-% !TeX root = Vorlage.tex
+% !TeX root = DigDes.tex
%% TODO: publish to CTAN
\documentclass[]{tex/hsrzf}
@@ -13,27 +13,28 @@
%% Language configuration
\usepackage{polyglossia}
-\setdefaultlanguage[variant=swiss]{german}
+% \setdefaultlanguage[variant=swiss]{german}
+\setdefaultlanguage{english}
%% License configuration
\usepackage[
type={CC},
modifier={by-nc-sa},
version={4.0},
- lang={german},
+ % lang={german},
]{doclicense}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Metadata
\course{Elektrotechnik}
-\module{ModAbk}
-\semester{Fr\"uhlingssemester 2020}
+\module{DigDes}
+\semester{Spring Semester 2021}
-\authoremail{vname@hsr.ch}
-\author{\textsl{Vorname Name} -- \texttt{\theauthoremail}}
+\authoremail{naoki.pross@ost.ch}
+\author{\textsl{Naoki Pross} -- \texttt{\theauthoremail}}
-\title{\texttt{\themodule} Zusammenfassung}
+\title{\texttt{\themodule}: Digital Design}
\date{\thesemester}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -44,15 +45,12 @@
\maketitle
\tableofcontents
-\section{Einf\"uhrung}
-\[
- i\hbar \partial_t \left| \psi(t) \right\rangle
- = \hat{H} \left| \psi(t) \right\rangle
-\]
-
-
-\section{Lizenz}
+\section{License}
\doclicenseThis
+\newpage
+
+% \section{Realisierungsformen digitaler Schaltungen}
+\input{tex/vhdl}
\end{document}
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
new file mode 100644
index 0000000..1854592
--- /dev/null
+++ b/tex/vhdl.tex
@@ -0,0 +1,42 @@
+\section{VHSIC Hardware Description Language (\texttt{VHDL})}
+
+\newcommand{\ph}[1]{\textrm{\textit{#1}}}
+\newcommand{\reqph}[1]{\textrm{\textlangle\,\ph{#1}\,\textrangle}}
+\newcommand{\optionalph}[1]{\textrm{[\,\ph{#1}\,]}}
+
+\subsection{Entities and Architectures}
+
+\begin{lstlisting}[language=vhdl]
+entity `\reqph{name}` is
+ port(
+ `\reqph{pin}` : `\reqph{mode} \reqph{type}`;
+ );
+end `\reqph{name}`;
+\end{lstlisting}
+
+\begin{lstlisting}[language=vhdl]
+architecture `\reqph{name}` of `\reqph{entity}` is
+ -- declare used variables, signals and component types
+begin
+ -- concurrent area
+end `\optionalph{name}`;
+\end{lstlisting}
+
+\subsection{Declaration}
+\begin{lstlisting}[language=vhdl]
+signal `\reqph{name}`, `\optionalph{name, \ldots}` : `\reqph{type}`;
+variable `\reqph{name}`, `\optionalph{name, \ldots}` : `\reqph{type}`;
+
+component `\reqph{entity name}` is
+ port(
+ `\ph{}`
+ );
+end component;
+\end{lstlisting}
+
+\subsection{Concurrent Area}
+
+\begin{lstlisting}[language=vhdl]
+`\optionalph{label}`: `\reqph{signal}` <= `\ph{Expression}`
+\end{lstlisting}
+