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-rw-r--r--DigDes.tex3
-rw-r--r--build/DigDes.pdfbin73543 -> 79903 bytes
-rw-r--r--tex/statemachines.tex64
-rw-r--r--tex/vhdl.tex39
4 files changed, 102 insertions, 4 deletions
diff --git a/DigDes.tex b/DigDes.tex
index e2fde28..5c7c011 100644
--- a/DigDes.tex
+++ b/DigDes.tex
@@ -66,7 +66,7 @@
\maketitle
\tableofcontents
-\section{License}
+\section*{License}
\doclicenseThis
% \newpage
@@ -74,5 +74,6 @@
% \section{Realisierungsformen digitaler Schaltungen}
\input{tex/vhdl}
+\input{tex/statemachines}
\end{document}
diff --git a/build/DigDes.pdf b/build/DigDes.pdf
index 50b490a..ed2b99f 100644
--- a/build/DigDes.pdf
+++ b/build/DigDes.pdf
Binary files differ
diff --git a/tex/statemachines.tex b/tex/statemachines.tex
new file mode 100644
index 0000000..181e593
--- /dev/null
+++ b/tex/statemachines.tex
@@ -0,0 +1,64 @@
+\section{State Machines}
+There are 3 types of state machines.
+\begin{center}
+ \ttfamily
+ \begin{tikzpicture}[
+ node distance = 3mm,
+ box/.style = {
+ draw = black, thick, fill = gray!20!white,
+ minimum width = 20mm, minimum height = 8mm,
+ }
+ ]
+
+ % mealey
+ \begin{scope}
+ \node[box] (G) {\large G};
+ \node[box, above = of G] (F) {\large F};
+ \node[box, below = of G] (Z) {\large Z};
+
+ \node[above = of F] {\large Mealey};
+
+ \draw[very thick, ->, hsr-blue] (F.east) -- ++(1,0) node[right] {oup};
+ \draw[very thick, ->, hsr-lakegreen] (G.east) -- ++(.5,0) |- (Z.east);
+ \draw[very thick, ->] (Z.west) -- ++(-.5,0) |- ($(G.west) - (0,.25)$);
+ \draw[very thick, ->] (G.west) ++ (-.5,-.25) |- ($(F.west) + (0,.25)$);
+
+ \draw[very thick, ->, hsr-mauve] ($(G.west) + (-1.5,.25)$)
+ node[left] {inp} -- ++(1.5,0);
+ \draw[very thick, ->, hsr-mauve] ($(G.west) + (-1,.25)$) |- ($(F.west) - (0,.25)$);
+ \end{scope}
+
+ % moore
+ \begin{scope}[yshift = -42mm]
+ \node[box] (G) {\large G};
+ \node[box, above = of G] (F) {\large F};
+ \node[box, below = of G] (Z) {\large Z};
+
+ \node[above = of F] {\large Moore};
+
+ \draw[very thick, ->, hsr-blue] (F.east) -- ++(1,0) node[right] {oup};
+ \draw[very thick, ->, hsr-lakegreen] (G.east) -- ++(.5,0) |- (Z.east);
+ \draw[very thick, ->] (Z.west) -- ++(-.5,0) |- ($(G.west) - (0,.25)$);
+ \draw[very thick, ->] (G.west) ++ (-.5,-.25) |- (F.west);
+
+ \draw[very thick, ->, hsr-mauve] ($(G.west) + (-1.5,.25)$)
+ node[left] {inp} -- ++(1.5,0);
+ \end{scope}
+
+ % Medwedjew
+ \begin{scope}[yshift = -80mm]
+ \node[box] (G) {\large G};
+ \node[box, below = of G] (Z) {\large Z};
+
+ \node[above = of G, yshift = 3mm] {\large Medwedjew};
+
+ \draw[very thick, ->, hsr-lakegreen] (G.east) -- ++(.5,0) |- (Z.east);
+ \draw[very thick, ->, hsr-blue] (Z.west) -- ++(-.5,0) |- ($(G.west) - (0,.25)$);
+ \draw[very thick, ->, hsr-blue] (G.west) ++ (-.5,-.25) |- ($(G.east) + (1,.75)$)
+ node[right] {oup};
+
+ \draw[very thick, ->, hsr-mauve] ($(G.west) + (-1.5,.25)$)
+ node[left] {inp} -- ++(1.5,0);
+ \end{scope}
+ \end{tikzpicture}
+\end{center}
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
index fc92da6..1c9cabc 100644
--- a/tex/vhdl.tex
+++ b/tex/vhdl.tex
@@ -150,10 +150,10 @@ component `\reqph{entity name}` is
);
end component;
\end{lstlisting}
-
-It is possible to create custom types, usually to create state machines.
+For entities with multiple architectures, it is possible to choose which
+architecture is used with the following expression.
\begin{lstlisting}[language=vhdl]
-type `\reqph{name}` is (`\reqph{identifier}`, `\reqph{identifier}`, `\ph{\ldots}`);
+for `\reqph{label or {\tt all}}`: use entity `\reqph{library}`.`\reqph{entity}`(`\reqph{architecture}`);
\end{lstlisting}
\subsection{Concurrent Area}
@@ -260,6 +260,33 @@ Higher level conditions can be written in two ways.
`\reqph{source}` when others;
\end{lstlisting}
+\subsubsection{Components}
+External components that have been previously declared, can be used with the
+\vhdl{port map(}\reqph{assignments}\texttt{)} syntax. For example:
+\begin{lstlisting}[language=vhdl]
+-- declaration
+component flipflop is
+ port(
+ clk, set, reset : in std_ulogic,
+ Q, Qn : out std_ulogic
+ );
+end component flipflop;
+
+signal clk_int, a, b : in std_ulogic;
+signal y, z : out std_ulogic;
+
+-- concurrent
+u1: flipflop
+ port map(
+ clk => clk_int,
+ set => a,
+ reset => b,
+ Q => y,
+ Qn => z
+ );
+
+\end{lstlisting}
+
\subsubsection{Processes}
For more sophisticated logic, VHDL offers a way of writing sequential
statements called \emph{processes}.
@@ -329,4 +356,10 @@ begin
end process;
\end{lstlisting}
+\subsection{Custom and arithmetic types}
+It is possible to create custom types, usually to create state machines.
+\begin{lstlisting}[language=vhdl]
+type `\reqph{name}` is (`\reqph{identifier}`, `\reqph{identifier}`, `\ph{\ldots}`);
+\end{lstlisting}
+
% vim:ts=2 sw=2 et: