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| -rw-r--r-- | build/DigDes.pdf | bin | 110141 -> 110140 bytes | |||
| -rw-r--r-- | tex/testbench.tex | 4 |
2 files changed, 3 insertions, 1 deletions
diff --git a/build/DigDes.pdf b/build/DigDes.pdf Binary files differindex 29b3b74..fb6c6ef 100644 --- a/build/DigDes.pdf +++ b/build/DigDes.pdf diff --git a/tex/testbench.tex b/tex/testbench.tex index 60e654b..d7fe70f 100644 --- a/tex/testbench.tex +++ b/tex/testbench.tex @@ -5,7 +5,9 @@ written by a \emph{test designer}. \subsection{Simulator} VHDL simulates digital systems using \emph{delta cycles}. -%% TODO: notes on how delta cycles work + +%% TODO: notes on how delta cycles work, read +%% https://stackoverflow.com/questions/43652630/delta-cycles-and-waveforms \subsection{Transport delay} To model a time delay of a signal there are two ways: |