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-rw-r--r--tex/model-hardware.tex51
-rw-r--r--tex/samples.tex77
-rw-r--r--tex/statemachines.tex2
-rw-r--r--tex/testbench.tex4
-rw-r--r--tex/vhdl.tex14
5 files changed, 134 insertions, 14 deletions
diff --git a/tex/model-hardware.tex b/tex/model-hardware.tex
index c0ccedc..010b414 100644
--- a/tex/model-hardware.tex
+++ b/tex/model-hardware.tex
@@ -128,10 +128,9 @@ the other axis while gravitating towards the origin (project goal).
\end{figure}
%% TODO: finish picture
-\iffalse
Figure \ref{fig:asic-design-flow} shows a typical flow diagram of how an ASIC device
is designed.
-\begin{figure}[h]
+\begin{figure}
\begin{tikzpicture}[
scale = .7,
font = \small\ttfamily,
@@ -142,6 +141,8 @@ is designed.
align = center,
text width = 2.1cm,
rounded corners = 5pt,
+ minimum height = 8mm,
+ outer sep = 1mm,
},
box/.style = {
rectangle,
@@ -149,6 +150,7 @@ is designed.
fill = lightgray!10,
align = center,
text width = 2.1cm,
+ outer sep = 1mm,
},
lib/.style = {
rectangle,
@@ -156,6 +158,7 @@ is designed.
fill = lightgray!10,
align = center,
text width = 2.1cm,
+ outer sep = 1mm,
},
ghost/.style = {
outer sep = 0,
@@ -169,16 +172,54 @@ is designed.
\node[ghost] (lineA) {}; & & \node[ghost] (lineB) {}; \\
\node[box] (tm) {Technology Mapping}; \\
\node[box] (ts) {Test Synthesis}; \\
- \node[bubble] (gates) {}; & \node[box] (pres) {Prelayout Simulation}; \\
+ \node[bubble] (gates) {Gates}; & \node[box] (pres) {Prelayout Simulation}; \\
\node[box] (l) {Layout}; & \node[box] (posts) {Postlayout Simulation}; \\
- \node[bubble] (design) {}; & & \node[lib] {Technology Library}; \\
+ \node[bubble] (design) {Hardware}; & & \node[lib] (tech) {Technology Library}; \\
};
+
+ \draw[thick, dashed, gray]
+ (lineA) to ++(-2,0)
+ (lineA) to (lineB) to ++(1,0)
+ node[rotate = 90, above = 5mm, anchor = west, text width = 3cm] {\bfseries Technology Indipendent}
+ node[rotate = 90, below = 25mm, anchor = west, text width = 3cm] {\bfseries Technology Dependent};
+
+ \begin{scope}[ultra thick, ->, lightgray]
+ \draw (tech) to[in = -40, out = 180] (l);
+ \draw (tech) to[in = -30, out = 160] (posts);
+ \draw (tech) to[in = 0, out = 75] (ts);
+ \draw (tech) to[in = 0, out = 60] (tm);
+ \draw (tech) to[in = -10, out = 90] (pres);
+ \end{scope}
+
+ \begin{scope}[thick, ->]
+ \draw (tbd) |- (fs);
+ \draw (tbd) |- (pres);
+ \draw (tbd) |- (posts);
+
+ \draw (se) -- (so);
+
+ \draw (dd) |- (fs);
+ \draw (dd) -- (so);
+ \draw (so) -- (tm);
+ \draw (tm) -- (ts);
+ \draw (ts) -- (gates);
+
+ \draw (gates) -- (pres);
+ \draw (gates) to[out = -45, in = 135] (posts);
+
+ \draw (gates) -- (l);
+ \draw (l) -- (design);
+ \draw (design) to[out = 0, in = -90] (posts);
+ \end{scope}
+
\end{tikzpicture}
\caption{
Design flow for an ASIC device.
\label{fig:asic-design-flow}
}
\end{figure}
-\fi
% \section{Hardware}
+%% TODO: hardware
+
+% vim:ts=2 sw=2 et:
diff --git a/tex/samples.tex b/tex/samples.tex
new file mode 100644
index 0000000..0e335d2
--- /dev/null
+++ b/tex/samples.tex
@@ -0,0 +1,77 @@
+\section{Samples / Templates}
+
+Below is a template for a simple VHDL file.
+
+\begin{lstlisting}[language=vhdl]
+library ieee;
+use ieee.std_logic_1164.all;
+-- declare entities (`\S\ref{sec:vhdl:entities-arch}`)
+entity `\reqph{name}` is
+ port(`\optionalph{pins}`);
+end entity `\reqph{name}`;
+-- declare architectures (`\S\ref{sec:vhdl:entities-arch}`)
+architecture `\reqph{name}` of `\reqph{entity name}` is
+ -- internal signals (`\S\ref{sec:vhdl:declarations}`)
+ -- other components (`\S\ref{sec:vhdl:components}`)
+ -- declare custom types (`\S\ref{sec:fsm:encode}`)
+ -- variables of custom type (`\S\ref{sec:fsm:encode}`)
+begin
+ -- assignments and processes (`\S\ref{sec:vhdl:concurrent}`)
+end architecture `\reqph{name}`;
+\end{lstlisting}
+And for a test bench
+\begin{lstlisting}[language=vhdl]
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- declare entities (`\S\ref{sec:vhdl:entities-arch}`)
+entity `\reqph{name}`_tb is
+ -- nothing here
+end entity `\reqph{name}`_tb;
+
+architecture tb of `\reqph{name}`_tb is
+ -- simulator settings
+ constant freq : natural := `\reqph{frequency}`;
+ constant time : time := 1 sec / freq;
+
+ -- component of DUT
+ component `\reqph{name}` is
+ port(
+ clk : in std_ulogic;
+ `\optionalph{other I/O}`
+ );
+ end component `\reqph{name}`;
+
+ signal clk_tb : std_ulogic;
+ -- more signals for inputs and outputs
+begin
+
+ dut: component `\reqph{name}`
+ port map(
+ clk => clk_tb;
+ `\reqph{other I/O}`);
+
+ clk_generator: process
+ -- generate clock (`\S\ref{sec:stimuli}`)
+ clk_tb <= '1'; wait for (T/2);
+ clk_tb <= '0'; wait for (T/2);
+ end process;
+
+ stimuli: process
+ begin
+ -- generate stimuli (`\S\ref{sec:stimuli}`)
+ -- for loops, after, etc.
+ end;
+
+ response: process
+ -- constants for expected outputs
+ begin
+ wait for 0.9 * T;
+ -- assertions (`\S\ref{sec:assertions}`)
+ wait for T;
+ end process;
+
+end architecture tb;
+
+\end{lstlisting}
+% vim:ts=2 sw=2 et:
diff --git a/tex/statemachines.tex b/tex/statemachines.tex
index 967737b..1e1546f 100644
--- a/tex/statemachines.tex
+++ b/tex/statemachines.tex
@@ -63,7 +63,7 @@
\end{tikzpicture}
\end{figure}
-\subsection{Encoding the state}
+\subsection{Encoding the state} \label{sec:fsm:encode}
For Mealey and Moore machines it is typical to write:
\begin{lstlisting}[language=vhdl]
type state_type is (st_rst, st_a, st_b, st_c, ...);
diff --git a/tex/testbench.tex b/tex/testbench.tex
index 5892820..71496f2 100644
--- a/tex/testbench.tex
+++ b/tex/testbench.tex
@@ -26,7 +26,7 @@ y <= `\reqph{expression}` after `\reqph{time}`;
\end{lstlisting}
%% TODO: tikz timing diagram
-\subsection{Generate stimuli}
+\subsection{Generate stimuli} \label{sec:stimuli}
Simple stimuli (signals) are generated using processes. For example a clock
signal done in three ways:
\begin{lstlisting}[language=vhdl]
@@ -99,7 +99,7 @@ for i in 0 to 2**n -1 loop
end loop;
\end{lstlisting}
-\subsection{Assertions}
+\subsection{Assertions} \label{sec:assertions}
Assertions are used write tests to check that a signal is in the correct state.
\begin{lstlisting}[language=vhdl]
`\optionalph{label}`: assert `\reqph{condition}` report `\reqph{string}` severity `\reqph{severity}`;
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
index 64bc9db..6cf160c 100644
--- a/tex/vhdl.tex
+++ b/tex/vhdl.tex
@@ -39,7 +39,7 @@ use `\reqph{library}`.`\reqph{element or {\tt all}}`;
use `\reqph{library}`.`\reqph{package}`.`\reqph{element or {\tt all}}`;
\end{lstlisting}
-\subsection{Entities and Architectures}
+\subsection{Entities and Architectures} \label{sec:vhdl:entities-arch}
In VHDL the concept of \emph{entity} describes a black box of which only
inputs and outputs are known. The internals of an entity are described through
an \emph{architecture}. There can be multiple architectures for a single entity.
@@ -205,7 +205,7 @@ support the operations in table \ref{tab:arithmetic-type-ops}.
- & Subtraction \\
abs() & Absolute value \\
* & Multiplication \\
- / & Division & Typically no \\
+ / & Division & Typically not available\\
** & Power & Only powers of 2 \\
mod & Modulo & Only modulo of \(2^k\) \\
rem & Remainder & Only of division by \(2^k\) \\
@@ -325,6 +325,8 @@ When the conversion is between signals with a different underlying type it is a
\fill[hsr-blue20]
(sr) to (ur) to (ur) |- (slvr) to (slvr) -| (sr) to cycle;
+
+ \node[above, hsr-blue80] at (slvr) {array types};
\end{pgfonlayer}
\draw[thick, ->]
@@ -354,7 +356,7 @@ When the conversion is between signals with a different underlying type it is a
\end{tikzpicture}
\end{figure}
-\subsection{Declarations} \label{sec:declarations}
+\subsection{Declarations} \label{sec:vhdl:declarations}
Before a \vhdl{begin} -- \vhdl{end} block, there is usually a list of declarations.
A self evident examples are \emph{constants}.
\begin{lstlisting}[language=vhdl]
@@ -388,7 +390,7 @@ architecture is used with the following expression.
for `\reqph{label or {\tt all}}`: use entity `\reqph{library}`.`\reqph{entity}`(`\reqph{architecture}`);
\end{lstlisting}
-\subsection{Concurrent Area}
+\subsection{Concurrent Area} \label{sec:vhdl:concurrent}
\begin{figure}[h]
\centering
\begin{tikzpicture}[
@@ -499,7 +501,7 @@ Higher level conditions can be written in two ways.
`\reqph{source}` when others;
\end{lstlisting}
-\subsubsection{Components}
+\subsubsection{Components} \label{sec:vhdl:components}
External components that have been previously declared can be used with the
\vhdl{port map(}\reqph{assignments}\texttt{)} syntax. For example:
\begin{lstlisting}[language=vhdl]
@@ -540,7 +542,7 @@ end process;
Processes have a \emph{sensitivity list} that can be empty. When a signal in
the sensitivity list changes state, the process is executed. With an empty
sensitivity list, the process runs continuously. In the declaration,
-everything from \S\ref{sec:declarations} applies. For the sequential
+everything from \S\ref{sec:vhdl:declarations} applies. For the sequential
statements, the following applies:
\begin{itemize}
\item Neither selective (\vhdl{with}) nor conditional (\vhdl{when}) should be used.