From 07c8c2a02f3755f179a7ea4bc7dcc2b1d56f6708 Mon Sep 17 00:00:00 2001
From: Nao Pross <np@0hm.ch>
Date: Thu, 20 May 2021 16:55:12 +0200
Subject: Start VHDL

---
 DigDes.tex   | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Vorlage.tex  | 58 ----------------------------------------------------------
 tex/vhdl.tex | 42 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 98 insertions(+), 58 deletions(-)
 create mode 100644 DigDes.tex
 delete mode 100644 Vorlage.tex
 create mode 100644 tex/vhdl.tex

diff --git a/DigDes.tex b/DigDes.tex
new file mode 100644
index 0000000..63d58aa
--- /dev/null
+++ b/DigDes.tex
@@ -0,0 +1,56 @@
+% !TeX program = xelatex
+% !TeX encoding = utf8
+% !TeX root = DigDes.tex
+
+%% TODO: publish to CTAN
+\documentclass[]{tex/hsrzf}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Packages
+
+%% TODO: publish to CTAN
+\usepackage{tex/hsrstud}
+
+%% Language configuration
+\usepackage{polyglossia}
+% \setdefaultlanguage[variant=swiss]{german}
+\setdefaultlanguage{english}
+
+%% License configuration
+\usepackage[
+    type={CC},
+    modifier={by-nc-sa},
+    version={4.0},
+    % lang={german},
+]{doclicense}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Metadata
+
+\course{Elektrotechnik}
+\module{DigDes}
+\semester{Spring Semester 2021}
+
+\authoremail{naoki.pross@ost.ch}
+\author{\textsl{Naoki Pross} -- \texttt{\theauthoremail}}
+
+\title{\texttt{\themodule}: Digital Design}
+\date{\thesemester}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Document
+
+\begin{document}
+
+\maketitle
+\tableofcontents
+
+\section{License}
+\doclicenseThis
+
+\newpage
+
+% \section{Realisierungsformen digitaler Schaltungen}
+\input{tex/vhdl}
+
+\end{document}
diff --git a/Vorlage.tex b/Vorlage.tex
deleted file mode 100644
index 10180b5..0000000
--- a/Vorlage.tex
+++ /dev/null
@@ -1,58 +0,0 @@
-% !TeX program = xelatex
-% !TeX encoding = utf8
-% !TeX root = Vorlage.tex
-
-%% TODO: publish to CTAN
-\documentclass[]{tex/hsrzf}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Packages
-
-%% TODO: publish to CTAN
-\usepackage{tex/hsrstud}
-
-%% Language configuration
-\usepackage{polyglossia}
-\setdefaultlanguage[variant=swiss]{german}
-
-%% License configuration
-\usepackage[
-    type={CC},
-    modifier={by-nc-sa},
-    version={4.0},
-    lang={german},
-]{doclicense}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Metadata
-
-\course{Elektrotechnik}
-\module{ModAbk}
-\semester{Fr\"uhlingssemester 2020}
-
-\authoremail{vname@hsr.ch}
-\author{\textsl{Vorname Name} -- \texttt{\theauthoremail}}
-
-\title{\texttt{\themodule} Zusammenfassung}
-\date{\thesemester}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% Document
-
-\begin{document}
-
-\maketitle
-\tableofcontents
-
-\section{Einf\"uhrung}
-\[
-  i\hbar \partial_t \left| \psi(t) \right\rangle 
-    = \hat{H} \left| \psi(t) \right\rangle
-\]
-
-
-\section{Lizenz}
-\doclicenseThis
-
-
-\end{document}
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
new file mode 100644
index 0000000..1854592
--- /dev/null
+++ b/tex/vhdl.tex
@@ -0,0 +1,42 @@
+\section{VHSIC Hardware Description Language (\texttt{VHDL})}
+
+\newcommand{\ph}[1]{\textrm{\textit{#1}}}
+\newcommand{\reqph}[1]{\textrm{\textlangle\,\ph{#1}\,\textrangle}}
+\newcommand{\optionalph}[1]{\textrm{[\,\ph{#1}\,]}}
+
+\subsection{Entities and Architectures}
+
+\begin{lstlisting}[language=vhdl]
+entity `\reqph{name}` is
+  port(
+    `\reqph{pin}` : `\reqph{mode} \reqph{type}`;
+  );
+end `\reqph{name}`;
+\end{lstlisting}
+
+\begin{lstlisting}[language=vhdl]
+architecture `\reqph{name}` of `\reqph{entity}` is
+  -- declare used variables, signals and component types
+begin
+  -- concurrent area
+end `\optionalph{name}`;
+\end{lstlisting}
+
+\subsection{Declaration}
+\begin{lstlisting}[language=vhdl]
+signal `\reqph{name}`, `\optionalph{name, \ldots}` : `\reqph{type}`;
+variable `\reqph{name}`, `\optionalph{name, \ldots}` : `\reqph{type}`;
+
+component `\reqph{entity name}` is
+  port(
+    `\ph{}`
+  );
+end component;
+\end{lstlisting}
+
+\subsection{Concurrent Area}
+
+\begin{lstlisting}[language=vhdl]
+`\optionalph{label}`: `\reqph{signal}` <= `\ph{Expression}`
+\end{lstlisting}
+
-- 
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