From 56527e5b0d62a962336a2ec5642afdba8c314b1b Mon Sep 17 00:00:00 2001
From: Nao Pross <np@0hm.ch>
Date: Fri, 21 May 2021 01:38:15 +0200
Subject: Fix typos
---
DigDes.tex | 5 ++++-
build/DigDes.pdf | Bin 88963 -> 89638 bytes
tex/statemachines.tex | 2 +-
tex/vhdl.tex | 14 ++++++++------
4 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/DigDes.tex b/DigDes.tex
index f61fdb5..b9033fe 100644
--- a/DigDes.tex
+++ b/DigDes.tex
@@ -72,8 +72,11 @@
% \newpage
\twocolumn
-% \section{Realisierungsformen digitaler Schaltungen}
+\section{Development model and Hardware}
+
\input{tex/vhdl}
\input{tex/statemachines}
+\section{Testbench}
+
\end{document}
diff --git a/build/DigDes.pdf b/build/DigDes.pdf
index b421210..2b23d7c 100644
Binary files a/build/DigDes.pdf and b/build/DigDes.pdf differ
diff --git a/tex/statemachines.tex b/tex/statemachines.tex
index d656569..9fb47e2 100644
--- a/tex/statemachines.tex
+++ b/tex/statemachines.tex
@@ -71,7 +71,7 @@ type state_type is (st_rst, st_a, st_b, st_c, ...);
signal present_state, next_state : state_type;
\end{lstlisting}
The encoding of the state is left automatically to the synthesizer or
-configured in the graphic interface of the tool. If a custom encoding is
+configured in the graphical interface of the tool. If a custom encoding is
required (Medwedjew), adding the following generates a custom encoding.
\begin{lstlisting}[language=vhdl]
attribute enum_encoding : string;
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
index 1c03873..e51b357 100644
--- a/tex/vhdl.tex
+++ b/tex/vhdl.tex
@@ -245,14 +245,15 @@ signal a, b : bit;
data = (1 => a, 0 => b, others => '0')
\end{lstlisting}
-\subsubsection{Seiective and conditional assignment}
+\subsubsection{Selective and conditional assignment}
Higher level conditions can be written in two ways.
\begin{lstlisting}[language=vhdl]
-- using when
`\optionalph{label}:` y <= `\reqph{source}` when `\reqph{condition}` else
`\reqph{source}` when `\reqph{condition}` else
`\reqph{source}` when `\reqph{condition}`;
-
+\end{lstlisting}
+\begin{lstlisting}[language=vhdl]
-- using with
`\optionalph{label}`: with `\reqph{signal}` select `\reqph{dest}` <=
`\reqph{source}` when `\reqph{value}`,
@@ -261,7 +262,7 @@ Higher level conditions can be written in two ways.
\end{lstlisting}
\subsubsection{Components}
-External components that have been previously declared, can be used with the
+External components that have been previously declared can be used with the
\vhdl{port map(}\reqph{assignments}\texttt{)} syntax. For example:
\begin{lstlisting}[language=vhdl]
-- declaration
@@ -274,7 +275,8 @@ end component flipflop;
signal clk_int, a, b : in std_ulogic;
signal y, z : out std_ulogic;
-
+\end{lstlisting}
+\begin{lstlisting}[language=vhdl]
-- concurrent
u1: flipflop
port map(
@@ -288,8 +290,8 @@ u1: flipflop
\end{lstlisting}
\subsubsection{Processes}
-For more sophisticated logic, VHDL offers a way of writing sequential
-statements called \emph{processes}.
+For more sophisticated logic VHDL offers a way of writing sequential statements
+called \emph{processes}.
\begin{lstlisting}[language=vhdl]
`\optionalph{label}:` process (`\optionalph{sensitivity list}`)
-- declarations
--
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