From ec4eef5be25505c7673959b708ce9a9b8eaf7f21 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Sat, 22 May 2021 02:35:19 +0200 Subject: Update TODO --- build/DigDes.pdf | Bin 110141 -> 110140 bytes tex/testbench.tex | 4 +++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/build/DigDes.pdf b/build/DigDes.pdf index 29b3b74..fb6c6ef 100644 Binary files a/build/DigDes.pdf and b/build/DigDes.pdf differ diff --git a/tex/testbench.tex b/tex/testbench.tex index 60e654b..d7fe70f 100644 --- a/tex/testbench.tex +++ b/tex/testbench.tex @@ -5,7 +5,9 @@ written by a \emph{test designer}. \subsection{Simulator} VHDL simulates digital systems using \emph{delta cycles}. -%% TODO: notes on how delta cycles work + +%% TODO: notes on how delta cycles work, read +%% https://stackoverflow.com/questions/43652630/delta-cycles-and-waveforms \subsection{Transport delay} To model a time delay of a signal there are two ways: -- cgit v1.2.1