From 35b98b57084d971e199502981f8f4c14db64875b Mon Sep 17 00:00:00 2001
From: Nao Pross <np@0hm.ch>
Date: Wed, 25 Aug 2021 18:56:06 +0200
Subject: Typos

---
 tex/testbench.tex | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'tex/testbench.tex')

diff --git a/tex/testbench.tex b/tex/testbench.tex
index 71496f2..dc52453 100644
--- a/tex/testbench.tex
+++ b/tex/testbench.tex
@@ -3,6 +3,8 @@ To simulate a digial circuit it is possible to write test benches using VHDL.
 The code in this section may no longer be synthetisable, and is usually
 written by a \emph{test designer}.
 
+%% TODO: Talk about DUT, with an image?
+
 \subsection{Simulator}
 VHDL simulates digital systems using \emph{delta cycles}.
 
@@ -106,7 +108,7 @@ Assertions are used write tests to check that a signal is in the correct state.
 \end{lstlisting}
 The \vhdl{report} and \vhdl{severity} are optional but strongly advised. The
 severity can take one of 4 values: \vhdl{note}, \vhdl{warning}, \vhdl{error},
-\vhdl{failure}. Simulations can be configured to stop in when an error of the
+\vhdl{failure}. Simulations can be configured to stop when an error of the
 desired severity occurrs. An example:
 \begin{lstlisting}[language=vhdl]
 assert (tb_y = '0') report "error at vector 11" severity error;
-- 
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