From ef2d6bad3d4735381f60fd6d5b1be149ef3cb4fc Mon Sep 17 00:00:00 2001
From: Nao Pross <np@0hm.ch>
Date: Fri, 30 Jul 2021 16:29:41 +0200
Subject: Add Y diagram
---
tex/model-hardware.tex | 184 +++++++++++++++++++++++++++++++++++++++++++++++++
tex/vhdl.tex | 6 +-
2 files changed, 187 insertions(+), 3 deletions(-)
create mode 100644 tex/model-hardware.tex
(limited to 'tex')
diff --git a/tex/model-hardware.tex b/tex/model-hardware.tex
new file mode 100644
index 0000000..df0a220
--- /dev/null
+++ b/tex/model-hardware.tex
@@ -0,0 +1,184 @@
+\section{Development model}
+The workflow for the development is show in figure
+\ref{fig:gajski-kuhn-ychart}. In the Gajski-Kuhn Y-model has 3 axis for the
+perspectives of the product. It is typical to start from the behavioral axis,
+by treating the systems as a black-box, and then to jump back and forth between
+the other axis while gravitating towards the origin (project goal).
+\begin{figure}[h]
+ \centering
+ \resizebox{\linewidth}{!}{
+ \begin{tikzpicture}[
+ font=\ttfamily,
+ ]
+ \draw[gray] node[
+ circle,
+ fill = gray,
+ minimum size = 2mm,
+ outer sep = 0,
+ inner sep = 0,
+ ] (O) at (0,0) {};
+
+ \foreach \r/\desc in {
+ 1/{Electrical},
+ 2/{Logic gates},
+ 3/{Register transfer},
+ 4/{Architecture},
+ 5/{System}
+ }{
+ \draw[gray, dashed] (O) circle (\r);
+ \draw[gray] (90:\r)
+ node[
+ above = 1mm,
+ align = center,
+ font = \small\ttfamily,
+ fill = white,
+ ] {\desc};
+ }
+
+ \draw[red, thick] (O) to ++(30:6)
+ node[
+ above = 3mm,
+ align = center,
+ text width = 2cm
+ ] {\textbf{Structural Perspective}};
+ \foreach \r/\desc in {
+ 1/{Transistors, Wires},
+ 2/{Gates, Latches, Flip-Flops},
+ 3/{ALUs, Registers, Memories},
+ 4/{Subblocks},
+ 5/{Top blocks, I/O}
+ } {
+ \draw[red] (30:\r)
+ node[
+ circle, minimum size = 2mm,
+ fill = red,
+ outer sep = 0,
+ inner sep = 0
+ ] {}
+ node[
+ below right = 2mm,
+ align = left,
+ font = \small\ttfamily,
+ fill = white,
+ ] {\desc};
+ }
+
+ \draw[blue, thick] (O) to ++(150:6)
+ node[
+ above = 3mm,
+ align = center,
+ text width = 2cm
+ ] {\textbf{Behavioral Perspective}};
+ \foreach \r/\desc in {
+ 1/{Transfer functions},
+ 2/{Truth tables, State graphs},
+ 3/{Data moves and operations},
+ 4/{Subtasks},
+ 5/{Algorithm}
+ } {
+ \draw[blue] (150:\r)
+ node[
+ circle, minimum size = 2mm,
+ fill = blue,
+ outer sep = 0,
+ inner sep = 0
+ ] {}
+ node[
+ below left = 2mm,
+ align = right,
+ font = \small\ttfamily,
+ fill = white,
+ ] {\desc};
+ }
+
+ \draw[green!60!black, thick] (O) to ++(270:6)
+ node[
+ below = 3mm,
+ align = center,
+ text width = 2cm
+ ] {\textbf{Physical Perspective}};
+ \foreach \r/\desc in {
+ 1/{Mask polygons, Detailed layout},
+ 2/{Standard cells, Macro cells},
+ 3/{Placement and routing},
+ 4/{Floorplan partitioning},
+ 5/{Chip or board}
+ } {
+ \draw[green!60!black] (270:\r)
+ node[
+ circle, minimum size = 2mm,
+ fill = green!60!black,
+ outer sep = 0,
+ inner sep = 0
+ ] {}
+ node[
+ right = 2mm,
+ align = left,
+ font = \small\ttfamily,
+ fill = white,
+ ] {\desc};
+ }
+
+ \end{tikzpicture}
+ }
+ \caption{
+ Gajski-Kuhn Y-chart.
+ \label{fig:gajski-kuhn-ychart}
+ }
+\end{figure}
+
+%% TODO: finish picture
+\iffalse
+Figure \ref{fig:asic-design-flow} shows a typical flow diagram of how an ASIC device
+is designed.
+\begin{figure}[h]
+ \begin{tikzpicture}[
+ scale = .7,
+ font = \small\ttfamily,
+ bubble/.style = {
+ rectangle,
+ draw = black, thick,
+ fill = lightgray!10,
+ align = center,
+ text width = 2.1cm,
+ rounded corners = 5pt,
+ },
+ box/.style = {
+ rectangle,
+ draw = black, thick,
+ fill = lightgray!10,
+ align = center,
+ text width = 2.1cm,
+ },
+ lib/.style = {
+ rectangle,
+ draw = black, gray, thick, dashed,
+ fill = lightgray!10,
+ align = center,
+ text width = 2.1cm,
+ },
+ ghost/.style = {
+ outer sep = 0,
+ inner sep = 0,
+ }
+ ]
+ \matrix[row sep = 5mm, column sep = 5mm]{
+ \node[bubble] (dd) {Design Description}; & & \node[bubble] (tbd) {Testbench Description}; \\
+ \node[ghost] (A) {}; & \node[box] (fs) {Functional Simulation}; \\
+ \node[box] (so) {Synthesis \& Optimization}; & \node[lib] (se) {Standard Elements}; \\
+ \node[ghost] (lineA) {}; & & \node[ghost] (lineB) {}; \\
+ \node[box] (tm) {Technology Mapping}; \\
+ \node[box] (ts) {Test Synthesis}; \\
+ \node[bubble] (gates) {}; & \node[box] (pres) {Prelayout Simulation}; \\
+ \node[box] (l) {Layout}; & \node[box] (posts) {Postlayout Simulation}; \\
+ \node[bubble] (design) {}; & & \node[lib] {Technology Library}; \\
+ };
+ \end{tikzpicture}
+ \caption{
+ Design flow for an ASIC device.
+ \label{fig:asic-design-flow}
+ }
+\end{figure}
+\fi
+
+% \section{Hardware}
diff --git a/tex/vhdl.tex b/tex/vhdl.tex
index cb2b389..6feb80e 100644
--- a/tex/vhdl.tex
+++ b/tex/vhdl.tex
@@ -47,13 +47,13 @@ an \emph{architecture}. There can be multiple architectures for a single entity.
\begin{figure}[h]
\centering
\begin{tikzpicture}[
+ font = \ttfamily,
node distance = 1mm,
pin/.style = {
draw = black, fill = white, circle, thick,
inner sep = 0pt, minimum size = 2mm,
},
]
- \ttfamily
\node[
rectangle, draw = black, thick, fill = gray!20!white,
minimum width = 4.5cm, minimum height = 4cm,
@@ -227,6 +227,7 @@ for `\reqph{label or {\tt all}}`: use entity `\reqph{library}`.`\reqph{entity}`(
\begin{figure}[h]
\centering
\begin{tikzpicture}[
+ font = \ttfamily,
node distance = 1mm,
pin/.style = {
draw = black, fill = white, circle, thick,
@@ -238,7 +239,6 @@ for `\reqph{label or {\tt all}}`: use entity `\reqph{library}`.`\reqph{entity}`(
align = center,
},
]
- \ttfamily
\node[
draw = black, rectangle, fill = gray!20!white, thick,
@@ -448,8 +448,8 @@ y <= y xor a;
\end{minipage}
\begin{minipage}{.4\linewidth}
\centering
- \ttfamily
\begin{tikzpicture}[
+ font = \ttfamily,
outer sep = 0mm, inner sep = 0mm,
comp/.style = {
rectangle, draw = black, thick, fill = gray!20!white,
--
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