From 5e8e628da03121323351e54e6866826288e4c4bd Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 4 May 2018 18:27:12 +0200 Subject: Implement most of basic HAL Oscillator: The oscillator is configured correctly. Interrupts: RX uart interrupts work. The global interrupt vector table is enabled. UART: RX features work. --- hal/confbits.hpp | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 hal/confbits.hpp (limited to 'hal/confbits.hpp') diff --git a/hal/confbits.hpp b/hal/confbits.hpp new file mode 100644 index 0000000..9af7023 --- /dev/null +++ b/hal/confbits.hpp @@ -0,0 +1,39 @@ +#ifndef CONFBITS_HPP +#define CONFBITS_HPP + +// DEVCFG3 +#pragma config FSRSSEL = PRIORITY_7 // Shadow Register Set Priority Select->SRS Priority 7 +#pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration->Allow only one reconfiguration +#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration->Allow only one reconfiguration +#pragma config FUSBIDIO = ON // USB USID Selection->Controlled by the USB Module +#pragma config FVBUSONIO = ON // USB VBUS ON Selection->Controlled by USB Module + +// DEVCFG2 +#pragma config FPLLIDIV = DIV_12 // PLL Input Divider->12x Divider +#pragma config FPLLMUL = MUL_24 // PLL Multiplier->24x Multiplier +#pragma config UPLLIDIV = DIV_12 // USB PLL Input Divider->12x Divider +#pragma config UPLLEN = OFF // USB PLL Enable->Disabled and Bypassed +#pragma config FPLLODIV = DIV_256 // System PLL Output Clock Divider->PLL Divide by 256 + +// DEVCFG1 +#pragma config FNOSC = FRCDIV // Oscillator Selection Bits->Fast RC Osc w/Div-by-N (FRCDIV) +#pragma config FSOSCEN = ON // Secondary Oscillator Enable->Enabled +#pragma config IESO = ON // Internal/External Switch Over->Enabled +#pragma config POSCMOD = OFF // Primary Oscillator Configuration->Primary osc disabled +#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin->Disabled +#pragma config FPBDIV = DIV_8 // Peripheral Clock Divisor->Pb_Clk is Sys_Clk/8 +#pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection->Clock Switch Disable, FSCM Disabled +#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler->1:1048576 +#pragma config WINDIS = OFF // Watchdog Timer Window Enable->Watchdog Timer is in Non-Window Mode +#pragma config FWDTEN = OFF // Watchdog Timer Enable->WDT Disabled (SWDTEN Bit Controls) +#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size->Window Size is 25% + +// DEVCFG0 +#pragma config DEBUG = OFF // Background Debugger Enable->Debugger is Disabled +#pragma config JTAGEN = ON // JTAG Enable->JTAG Port Enabled +#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select->Communicate on PGEC1/PGED1 +#pragma config PWP = OFF // Program Flash Write Protect->Disable +#pragma config BWP = OFF // Boot Flash Write Protect bit->Protection Disabled +#pragma config CP = OFF // Code Protect->Protection Disabled + +#endif \ No newline at end of file -- cgit v1.2.1