Merge branch 'master' of https://git.thearcway.org/git/naopross/Xilofono

6 files changed, 0 insertions, 862 deletions

diff --git a/src/dist/default/debug/src.debug.lst b/src/dist/default/debug/src.debug.lst
deleted file mode 100644
index e69de29..0000000
--- a/src/dist/default/debug/src.debug.lst
+++ /dev/null
diff --git a/src/dist/default/debug/src.debug.map b/src/dist/default/debug/src.debug.map
deleted file mode 100644
index e69de29..0000000
--- a/src/dist/default/debug/src.debug.map
+++ /dev/null
diff --git a/src/dist/default/debug/src.debug.obj b/src/dist/default/debug/src.debug.obj
deleted file mode 100644
index e391aed..0000000
--- a/src/dist/default/debug/src.debug.obj
+++ /dev/null
diff --git a/src/dist/default/debug/src.debug.rlf b/src/dist/default/debug/src.debug.rlf
deleted file mode 100644
index 8586f2a..0000000
--- a/src/dist/default/debug/src.debug.rlf
+++ /dev/null
diff --git a/src/dist/default/debug/src.debug.sdb b/src/dist/default/debug/src.debug.sdb
deleted file mode 100644
index cf91952..0000000
--- a/src/dist/default/debug/src.debug.sdb
+++ /dev/null
@@ -1,520 +0,0 @@
-[p LITE_MODE AUTOSTATIC LFSROK EMI_WORD ]
-[d version 1.1 ]
-[d edition pro ]
-[d chip 18F45K22 ]
-[d frameptr 4065 ]
-"237 Z:\SAMB_4\projects\xilofono\src\main.c
-[e E43 . `uc
-C 0
-D 1
-E 2
-F 3
-G 4
-A 5
-B 6
-]
-"41 Z:\SAMB_4\projects\xilofono\src\midi.c
-[e E40 . `uc
-NOTE_ON 8
-NOTE_OFF 9
-POLYPHONIC_KEYPRESS 10
-CONTROLLER 11
-PROGRAM_CHANGE 12
-CHANNEL_PRESSURE 13
-PITCH_BLEND 15
-]
-"63
-[e E31 . `uc
-C 0
-D 1
-E 2
-F 3
-G 4
-A 5
-B 6
-]
-"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\float.c
-[v ___ftpack __ftpack `(f  1 e 3 0 ]
-"86 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftadd.c
-[v ___ftadd __ftadd `(f  1 e 3 0 ]
-"54 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftdiv.c
-[v ___ftdiv __ftdiv `(f  1 e 3 0 ]
-"62 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftmul.c
-[v ___ftmul __ftmul `(f  1 e 3 0 ]
-"20 C:\Program Files\Microchip\xc8\v1.44\sources\common\ftsub.c
-[v ___ftsub __ftsub `(f  1 e 3 0 ]
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c
-[v _memset memset `(*.39v  1 e 2 0 ]
-"10 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcadd.c
-[v ___fladd __fladd `(d  1 e 3 0 ]
-"245
-[v ___flsub __flsub `(d  1 e 3 0 ]
-"11 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcdiv.c
-[v ___fldiv __fldiv `(d  1 e 3 0 ]
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\sprcmul.c
-[v ___flmul __flmul `(d  1 e 3 0 ]
-"15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c
-[v ___lmul __lmul `(ul  1 e 4 0 ]
-"114 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _isr isr `II(v  1 e 1 0 ]
-"155
-[v _init_hw init_hw `T(v  1 e 1 0 ]
-"220
-[v _main main `(v  1 e 1 0 ]
-"266
-[v _eusart_write_midi eusart_write_midi `(i  1 e 2 0 ]
-"40 Z:\SAMB_4\projects\xilofono\src\midi.c
-[v _midi_set_status midi_set_status `(i  1 e 2 0 ]
-"51
-[v _midi_set_channel midi_set_channel `(i  1 e 2 0 ]
-"62
-[v _midi_note_on midi_note_on `(i  1 e 2 0 ]
-"4 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart1_init eusart1_init `(v  1 e 1 0 ]
-"25
-[v _eusart2_init eusart2_init `(v  1 e 1 0 ]
-"47
-[v _eusart1_putch eusart1_putch `(v  1 e 1 0 ]
-"53
-[v _eusart2_putch eusart2_putch `(v  1 e 1 0 ]
-"59
-[v _eusart1_getch eusart1_getch `(uc  1 e 1 0 ]
-"50 C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
-[v _ANSELA ANSELA `VEuc  1 e 1 @3896 ]
-"95
-[v _ANSELB ANSELB `VEuc  1 e 1 @3897 ]
-"145
-[v _ANSELC ANSELC `VEuc  1 e 1 @3898 ]
-"196
-[v _ANSELD ANSELD `VEuc  1 e 1 @3899 ]
-[s S467 . 1 `uc 1 ABDEN 1 0 :1:0 
-`uc 1 WUE 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 BRG16 1 0 :1:3 
-`uc 1 CKTXP 1 0 :1:4 
-`uc 1 DTRXP 1 0 :1:5 
-`uc 1 RCIDL 1 0 :1:6 
-`uc 1 ABDOVF 1 0 :1:7 
-]
-"4328
-[s S476 . 1 `uc 1 . 1 0 :4:0 
-`uc 1 SCKP 1 0 :1:4 
-]
-[s S716 . 1 `uc 1 ABDEN2 1 0 :1:0 
-`uc 1 WUE2 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 BRG162 1 0 :1:3 
-`uc 1 SCKP2 1 0 :1:4 
-`uc 1 DTRXP2 1 0 :1:5 
-`uc 1 RCIDL2 1 0 :1:6 
-`uc 1 ABDOVF2 1 0 :1:7 
-]
-[s S725 . 1 `uc 1 . 1 0 :4:0 
-`uc 1 TXCKP2 1 0 :1:4 
-`uc 1 RXDTP2 1 0 :1:5 
-`uc 1 RCMT2 1 0 :1:6 
-]
-[u S730 . 1 `S467 1 . 1 0 `S476 1 . 1 0 `S716 1 . 1 0 `S725 1 . 1 0 ]
-[v _BAUDCON2bits BAUDCON2bits `VES730  1 e 1 @3952 ]
-[s S395 . 1 `uc 1 RX9D 1 0 :1:0 
-`uc 1 OERR 1 0 :1:1 
-`uc 1 FERR 1 0 :1:2 
-`uc 1 ADDEN 1 0 :1:3 
-`uc 1 CREN 1 0 :1:4 
-`uc 1 SREN 1 0 :1:5 
-`uc 1 RX9 1 0 :1:6 
-`uc 1 SPEN 1 0 :1:7 
-]
-"4593
-[s S404 . 1 `uc 1 . 1 0 :3:0 
-`uc 1 ADEN 1 0 :1:3 
-]
-[s S651 . 1 `uc 1 RX9D2 1 0 :1:0 
-`uc 1 OERR2 1 0 :1:1 
-`uc 1 FERR2 1 0 :1:2 
-`uc 1 ADDEN2 1 0 :1:3 
-`uc 1 CREN2 1 0 :1:4 
-`uc 1 SREN2 1 0 :1:5 
-`uc 1 RX92 1 0 :1:6 
-`uc 1 SPEN2 1 0 :1:7 
-]
-[s S660 . 1 `uc 1 RCD82 1 0 :1:0 
-`uc 1 . 1 0 :5:1 
-`uc 1 RC8_92 1 0 :1:6 
-]
-[s S664 . 1 `uc 1 . 1 0 :6:0 
-`uc 1 RC92 1 0 :1:6 
-]
-[u S667 . 1 `S395 1 . 1 0 `S404 1 . 1 0 `S651 1 . 1 0 `S660 1 . 1 0 `S664 1 . 1 0 ]
-[v _RCSTA2bits RCSTA2bits `VES667  1 e 1 @3953 ]
-[s S346 . 1 `uc 1 TX9D 1 0 :1:0 
-`uc 1 TRMT 1 0 :1:1 
-`uc 1 BRGH 1 0 :1:2 
-`uc 1 SENDB 1 0 :1:3 
-`uc 1 SYNC 1 0 :1:4 
-`uc 1 TXEN 1 0 :1:5 
-`uc 1 TX9 1 0 :1:6 
-`uc 1 CSRC 1 0 :1:7 
-]
-"4873
-[s S599 . 1 `uc 1 TX9D2 1 0 :1:0 
-`uc 1 TRMT2 1 0 :1:1 
-`uc 1 BRGH2 1 0 :1:2 
-`uc 1 SENDB2 1 0 :1:3 
-`uc 1 SYNC2 1 0 :1:4 
-`uc 1 TXEN2 1 0 :1:5 
-`uc 1 TX92 1 0 :1:6 
-`uc 1 CSRC2 1 0 :1:7 
-]
-[s S608 . 1 `uc 1 TXD82 1 0 :1:0 
-`uc 1 . 1 0 :5:1 
-`uc 1 TX8_92 1 0 :1:6 
-]
-[u S612 . 1 `S346 1 . 1 0 `S599 1 . 1 0 `S608 1 . 1 0 ]
-[v _TXSTA2bits TXSTA2bits `VES612  1 e 1 @3954 ]
-"5093
-[v _TX2REG TX2REG `VEuc  1 e 1 @3955 ]
-"5164
-[v _SPBRG2 SPBRG2 `VEuc  1 e 1 @3957 ]
-"5202
-[v _SPBRGH2 SPBRGH2 `VEuc  1 e 1 @3958 ]
-"6278
-[v _PORTA PORTA `VEuc  1 e 1 @3968 ]
-"6563
-[v _PORTB PORTB `VEuc  1 e 1 @3969 ]
-"8058
-[v _TRISA TRISA `VEuc  1 e 1 @3986 ]
-"8280
-[v _TRISB TRISB `VEuc  1 e 1 @3987 ]
-[s S550 . 1 `uc 1 TRISC0 1 0 :1:0 
-`uc 1 TRISC1 1 0 :1:1 
-`uc 1 TRISC2 1 0 :1:2 
-`uc 1 TRISC3 1 0 :1:3 
-`uc 1 TRISC4 1 0 :1:4 
-`uc 1 TRISC5 1 0 :1:5 
-`uc 1 TRISC6 1 0 :1:6 
-`uc 1 TRISC7 1 0 :1:7 
-]
-"8534
-[s S559 . 1 `uc 1 RC0 1 0 :1:0 
-`uc 1 RC1 1 0 :1:1 
-`uc 1 RC2 1 0 :1:2 
-`uc 1 RC3 1 0 :1:3 
-`uc 1 RC4 1 0 :1:4 
-`uc 1 RC5 1 0 :1:5 
-`uc 1 RC6 1 0 :1:6 
-`uc 1 RC7 1 0 :1:7 
-]
-[u S568 . 1 `S550 1 . 1 0 `S559 1 . 1 0 ]
-[v _TRISCbits TRISCbits `VES568  1 e 1 @3988 ]
-[s S762 . 1 `uc 1 TRISD0 1 0 :1:0 
-`uc 1 TRISD1 1 0 :1:1 
-`uc 1 TRISD2 1 0 :1:2 
-`uc 1 TRISD3 1 0 :1:3 
-`uc 1 TRISD4 1 0 :1:4 
-`uc 1 TRISD5 1 0 :1:5 
-`uc 1 TRISD6 1 0 :1:6 
-`uc 1 TRISD7 1 0 :1:7 
-]
-"8756
-[s S771 . 1 `uc 1 RD0 1 0 :1:0 
-`uc 1 RD1 1 0 :1:1 
-`uc 1 RD2 1 0 :1:2 
-`uc 1 RD3 1 0 :1:3 
-`uc 1 RD4 1 0 :1:4 
-`uc 1 RD5 1 0 :1:5 
-`uc 1 RD6 1 0 :1:6 
-`uc 1 RD7 1 0 :1:7 
-]
-[u S780 . 1 `S762 1 . 1 0 `S771 1 . 1 0 ]
-[v _TRISDbits TRISDbits `VES780  1 e 1 @3989 ]
-[s S102 . 1 `uc 1 TUN 1 0 :6:0 
-`uc 1 PLLEN 1 0 :1:6 
-`uc 1 INTSRC 1 0 :1:7 
-]
-"9082
-[s S106 . 1 `uc 1 TUN0 1 0 :1:0 
-`uc 1 TUN1 1 0 :1:1 
-`uc 1 TUN2 1 0 :1:2 
-`uc 1 TUN3 1 0 :1:3 
-`uc 1 TUN4 1 0 :1:4 
-`uc 1 TUN5 1 0 :1:5 
-]
-[u S113 . 1 `S102 1 . 1 0 `S106 1 . 1 0 ]
-[v _OSCTUNEbits OSCTUNEbits `VES113  1 e 1 @3995 ]
-[s S195 . 1 `uc 1 TMR1IE 1 0 :1:0 
-`uc 1 TMR2IE 1 0 :1:1 
-`uc 1 CCP1IE 1 0 :1:2 
-`uc 1 SSP1IE 1 0 :1:3 
-`uc 1 TX1IE 1 0 :1:4 
-`uc 1 RC1IE 1 0 :1:5 
-`uc 1 ADIE 1 0 :1:6 
-]
-"9434
-[s S203 . 1 `uc 1 . 1 0 :3:0 
-`uc 1 SSPIE 1 0 :1:3 
-`uc 1 TXIE 1 0 :1:4 
-`uc 1 RCIE 1 0 :1:5 
-]
-[u S208 . 1 `S195 1 . 1 0 `S203 1 . 1 0 ]
-[v _PIE1bits PIE1bits `VES208  1 e 1 @3997 ]
-[s S21 . 1 `uc 1 TMR1IF 1 0 :1:0 
-`uc 1 TMR2IF 1 0 :1:1 
-`uc 1 CCP1IF 1 0 :1:2 
-`uc 1 SSP1IF 1 0 :1:3 
-`uc 1 TX1IF 1 0 :1:4 
-`uc 1 RC1IF 1 0 :1:5 
-`uc 1 ADIF 1 0 :1:6 
-]
-"9511
-[s S29 . 1 `uc 1 . 1 0 :3:0 
-`uc 1 SSPIF 1 0 :1:3 
-`uc 1 TXIF 1 0 :1:4 
-`uc 1 RCIF 1 0 :1:5 
-]
-[u S34 . 1 `S21 1 . 1 0 `S29 1 . 1 0 ]
-[v _PIR1bits PIR1bits `VES34  1 e 1 @3998 ]
-"10396
-[s S407 . 1 `uc 1 RX9D1 1 0 :1:0 
-`uc 1 OERR1 1 0 :1:1 
-`uc 1 FERR1 1 0 :1:2 
-`uc 1 ADDEN1 1 0 :1:3 
-`uc 1 CREN1 1 0 :1:4 
-`uc 1 SREN1 1 0 :1:5 
-`uc 1 RX91 1 0 :1:6 
-`uc 1 SPEN1 1 0 :1:7 
-]
-[s S416 . 1 `uc 1 RCD8 1 0 :1:0 
-`uc 1 . 1 0 :5:1 
-`uc 1 RC8_9 1 0 :1:6 
-]
-[s S420 . 1 `uc 1 . 1 0 :6:0 
-`uc 1 RC9 1 0 :1:6 
-]
-[s S423 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 SRENA 1 0 :1:5 
-]
-[u S426 . 1 `S395 1 . 1 0 `S404 1 . 1 0 `S407 1 . 1 0 `S416 1 . 1 0 `S420 1 . 1 0 `S423 1 . 1 0 ]
-[v _RCSTA1bits RCSTA1bits `VES426  1 e 1 @4011 ]
-"10840
-[s S355 . 1 `uc 1 TX9D1 1 0 :1:0 
-`uc 1 TRMT1 1 0 :1:1 
-`uc 1 BRGH1 1 0 :1:2 
-`uc 1 SENDB1 1 0 :1:3 
-`uc 1 SYNC1 1 0 :1:4 
-`uc 1 TXEN1 1 0 :1:5 
-`uc 1 TX91 1 0 :1:6 
-`uc 1 CSRC1 1 0 :1:7 
-]
-[s S364 . 1 `uc 1 TXD8 1 0 :1:0 
-`uc 1 . 1 0 :5:1 
-`uc 1 TX8_9 1 0 :1:6 
-]
-[u S368 . 1 `S346 1 . 1 0 `S355 1 . 1 0 `S364 1 . 1 0 ]
-[v _TXSTA1bits TXSTA1bits `VES368  1 e 1 @4012 ]
-"11183
-[v _TX1REG TX1REG `VEuc  1 e 1 @4013 ]
-"11261
-[v _RC1REG RC1REG `VEuc  1 e 1 @4014 ]
-"11330
-[v _SPBRG1 SPBRG1 `VEuc  1 e 1 @4015 ]
-"11408
-[v _SPBRGH1 SPBRGH1 `VEuc  1 e 1 @4016 ]
-"12436
-[s S479 . 1 `uc 1 ABDEN1 1 0 :1:0 
-`uc 1 WUE1 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 BRG161 1 0 :1:3 
-`uc 1 SCKP1 1 0 :1:4 
-`uc 1 DTRXP1 1 0 :1:5 
-`uc 1 RCIDL1 1 0 :1:6 
-`uc 1 ABDOVF1 1 0 :1:7 
-]
-[s S488 . 1 `uc 1 . 1 0 :4:0 
-`uc 1 TXCKP 1 0 :1:4 
-`uc 1 RXDTP 1 0 :1:5 
-`uc 1 RCMT 1 0 :1:6 
-]
-[s S493 . 1 `uc 1 . 1 0 :4:0 
-`uc 1 TXCKP1 1 0 :1:4 
-`uc 1 RXDTP1 1 0 :1:5 
-`uc 1 RCMT1 1 0 :1:6 
-]
-[s S498 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 RXCKP 1 0 :1:5 
-]
-[s S501 . 1 `uc 1 . 1 0 :1:0 
-`uc 1 W4E 1 0 :1:1 
-]
-[u S504 . 1 `S467 1 . 1 0 `S476 1 . 1 0 `S479 1 . 1 0 `S488 1 . 1 0 `S493 1 . 1 0 `S498 1 . 1 0 `S501 1 . 1 0 ]
-[v _BAUDCON1bits BAUDCON1bits `VES504  1 e 1 @4024 ]
-[s S167 . 1 `uc 1 T2CKPS 1 0 :2:0 
-`uc 1 TMR2ON 1 0 :1:2 
-`uc 1 T2OUTPS 1 0 :4:3 
-]
-"13217
-[s S171 . 1 `uc 1 T2CKPS0 1 0 :1:0 
-`uc 1 T2CKPS1 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 T2OUTPS0 1 0 :1:3 
-`uc 1 T2OUTPS1 1 0 :1:4 
-`uc 1 T2OUTPS2 1 0 :1:5 
-`uc 1 T2OUTPS3 1 0 :1:6 
-]
-[u S179 . 1 `S167 1 . 1 0 `S171 1 . 1 0 ]
-[v _T2CONbits T2CONbits `VES179  1 e 1 @4026 ]
-"13267
-[v _PR2 PR2 `VEuc  1 e 1 @4027 ]
-[s S128 . 1 `uc 1 SCS 1 0 :2:0 
-`uc 1 HFIOFS 1 0 :1:2 
-`uc 1 OSTS 1 0 :1:3 
-`uc 1 IRCF 1 0 :3:4 
-`uc 1 IDLEN 1 0 :1:7 
-]
-"16033
-[s S134 . 1 `uc 1 SCS0 1 0 :1:0 
-`uc 1 SCS1 1 0 :1:1 
-`uc 1 IOFS 1 0 :1:2 
-`uc 1 . 1 0 :1:3 
-`uc 1 IRCF0 1 0 :1:4 
-`uc 1 IRCF1 1 0 :1:5 
-`uc 1 IRCF2 1 0 :1:6 
-]
-[u S142 . 1 `S128 1 . 1 0 `S134 1 . 1 0 ]
-[v _OSCCONbits OSCCONbits `VES142  1 e 1 @4051 ]
-[s S53 . 1 `uc 1 RBIF 1 0 :1:0 
-`uc 1 INT0IF 1 0 :1:1 
-`uc 1 TMR0IF 1 0 :1:2 
-`uc 1 RBIE 1 0 :1:3 
-`uc 1 INT0IE 1 0 :1:4 
-`uc 1 TMR0IE 1 0 :1:5 
-`uc 1 PEIE_GIEL 1 0 :1:6 
-`uc 1 GIE_GIEH 1 0 :1:7 
-]
-"16922
-[s S62 . 1 `uc 1 . 1 0 :1:0 
-`uc 1 INT0F 1 0 :1:1 
-`uc 1 T0IF 1 0 :1:2 
-`uc 1 . 1 0 :1:3 
-`uc 1 INT0E 1 0 :1:4 
-`uc 1 T0IE 1 0 :1:5 
-`uc 1 PEIE 1 0 :1:6 
-`uc 1 GIE 1 0 :1:7 
-]
-[s S71 . 1 `uc 1 . 1 0 :6:0 
-`uc 1 GIEL 1 0 :1:6 
-`uc 1 GIEH 1 0 :1:7 
-]
-[u S75 . 1 `S53 1 . 1 0 `S62 1 . 1 0 `S71 1 . 1 0 ]
-[v _INTCONbits INTCONbits `VES75  1 e 1 @4082 ]
-"18736
-[v _RC1IF RC1IF `VEb  1 e 0 @31989 ]
-"19488
-[v _TX1IF TX1IF `VEb  1 e 0 @31988 ]
-"19496
-[v _TX2IF TX2IF `VEb  1 e 0 @32036 ]
-"106 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _keys_data keys_data `VE[16]ul  1 e 64 0 ]
-"108
-[v _keypresses keypresses `VEui  1 e 2 0 ]
-"220
-[v _main main `(v  1 e 1 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0 
-`uc 1 channel 1 0 :4:4 
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"223
-[v main@message message `S233  1 a 7 7 ]
-"222
-[v main@i i `ui  1 a 2 5 ]
-"263
-} 0
-"62 Z:\SAMB_4\projects\xilofono\src\midi.c
-[v _midi_note_on midi_note_on `(i  1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0 
-`uc 1 channel 1 0 :4:4 
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_note_on@pkt pkt `*.39S233  1 p 2 46 ]
-[v midi_note_on@channel channel `ui  1 p 2 48 ]
-[v midi_note_on@note note `E31  1 p 1 50 ]
-[v midi_note_on@velocity velocity `uc  1 p 1 51 ]
-"85
-} 0
-"40
-[v _midi_set_status midi_set_status `(i  1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0 
-`uc 1 channel 1 0 :4:4 
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_status@pkt pkt `*.39S233  1 p 2 41 ]
-[v midi_set_status@status status `E40  1 p 1 43 ]
-"49
-} 0
-"51
-[v _midi_set_channel midi_set_channel `(i  1 e 2 0 ]
-{
-[s S233 . 7 `uc 1 status 1 0 :4:0 
-`uc 1 channel 1 0 :4:4 
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_channel@pkt pkt `*.39S233  1 p 2 41 ]
-[v midi_set_channel@channel channel `ui  1 p 2 43 ]
-"60
-} 0
-"8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c
-[v _memset memset `(*.39v  1 e 2 0 ]
-{
-"15
-[v memset@p p `*.39uc  1 a 2 47 ]
-"8
-[v memset@p1 p1 `*.39v  1 p 2 41 ]
-[v memset@c c `i  1 p 2 43 ]
-[v memset@n n `ui  1 p 2 45 ]
-"22
-} 0
-"155 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _init_hw init_hw `T(v  1 e 1 0 ]
-{
-"216
-} 0
-"25 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart2_init eusart2_init `(v  1 e 1 0 ]
-{
-"45
-} 0
-"4
-[v _eusart1_init eusart1_init `(v  1 e 1 0 ]
-{
-"23
-} 0
-"266 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _eusart_write_midi eusart_write_midi `(i  1 e 2 0 ]
-{
-"269
-[v eusart_write_midi@data data `*.39uc  1 a 2 48 ]
-"268
-[v eusart_write_midi@length length `ui  1 a 2 46 ]
-[s S233 . 7 `uc 1 status 1 0 :4:0 
-`uc 1 channel 1 0 :4:4 
-`ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"266
-[v eusart_write_midi@pkt pkt `*.39CS233  1 p 2 42 ]
-"285
-} 0
-"53 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _eusart2_putch eusart2_putch `(v  1 e 1 0 ]
-{
-[v eusart2_putch@c c `uc  1 a 1 wreg ]
-[v eusart2_putch@c c `uc  1 a 1 wreg ]
-[v eusart2_putch@c c `uc  1 a 1 41 ]
-"57
-} 0
-"114 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _isr isr `II(v  1 e 1 0 ]
-{
-"116
-[v isr@i i `uc  1 a 1 40 ]
-[v isr@data_b data_b `uc  1 a 1 37 ]
-[v isr@data_a data_a `uc  1 a 1 36 ]
-"152
-} 0
diff --git a/src/dist/default/debug/src.debug.sym b/src/dist/default/debug/src.debug.sym
deleted file mode 100644
index c440798..0000000
--- a/src/dist/default/debug/src.debug.sym
+++ /dev/null
@@ -1,342 +0,0 @@
-__end_of_eusart2_putch 7D38 0 CODE 0
-__CFG_XINST$OFF 0 0 ABS 0
-_PR2 FBB 0 ABS 0
-__S0 8000 0 ABS 0
-__S1 B0 0 ABS 0
-__Hintentry 0 0 ABS 0
-__Lintentry 0 0 ABS 0
-midi_set_channel@pkt 2A 0 COMRAM 1
-__end_of_init_hw 7E52 0 CODE 0
-_isr 2 0 CODE 0
-__end_of_eusart_write_midi 7F28 0 CODE 0
-_eusart2_putch 7D2C 0 CODE 0
-isr@i 29 0 COMRAM 1
-_main 7F28 0 CODE 0
-___sp 0 0 STACK 2
-btemp 35 0 COMRAM 1
-start 2FA 0 CODE 0
-__size_of_eusart1_init 0 0 ABS 0
-__size_of_eusart2_init 0 0 ABS 0
-eusart_write_midi@pkt 2B 0 COMRAM 1
-eusart2_putch@c 2A 0 COMRAM 1
-_RC1IF 7CF5 0 ABS 0
-_TX1IF 7CF4 0 ABS 0
-_TX2IF 7D24 0 ABS 0
-isr@data_a 25 0 COMRAM 1
-_TRISA F92 0 ABS 0
-_TRISB F93 0 ABS 0
-_PORTA F80 0 ABS 0
-_PORTB F81 0 ABS 0
-__Hirdata 0 0 CODE 0
-__Lirdata 0 0 CODE 0
-__HRAM 0 0 ABS 0
-__LRAM 1 0 ABS 0
-isr@data_b 26 0 COMRAM 1
-wtemp6 36 0 COMRAM 1
-__CFG_WDTPS$32768 0 0 ABS 0
-__Hconfig 0 0 CONFIG 0
-__Lconfig 0 0 CONFIG 0
-__CFG_FOSC$INTIO67 0 0 ABS 0
-main@i A7 0 BANK0 1
-__Hbigram 0 0 ABS 0
-__Lbigram 0 0 ABS 0
-__Hrparam 0 0 ABS 0
-__Lrparam 0 0 ABS 0
-__Hram 0 0 ABS 0
-__Lram 0 0 ABS 0
-__Hcomram 0 0 ABS 0
-__Lcomram 0 0 ABS 0
-__Hsfr 0 0 ABS 0
-__Lsfr 0 0 ABS 0
-__size_of_isr 0 0 ABS 0
-eusart_write_midi@data 31 0 COMRAM 1
-__Hbss 0 0 RAM 1
-__CFG_STVREN$ON 0 0 ABS 0
-__Lbss 0 0 RAM 1
-___param_bank 0 0 ABS 0
-__Hnvrram 0 0 COMRAM 1
-__Lnvrram 0 0 COMRAM 1
-int$flags 35 0 COMRAM 1
-__size_of_midi_note_on 0 0 ABS 0
-_SPBRG1 FAF 0 ABS 0
-_SPBRG2 F75 0 ABS 0
-_PIE1bits F9D 0 ABS 0
-__Heeprom_data 0 0 EEDATA 0
-__Leeprom_data 0 0 EEDATA 0
-_PIR1bits F9E 0 ABS 0
-__Hintsave_regs 0 0 BIGRAM 1
-__Lintsave_regs 0 0 BIGRAM 1
-_ANSELA F38 0 ABS 0
-_ANSELB F39 0 ABS 0
-_RC1REG FAE 0 ABS 0
-_ANSELC F3A 0 ABS 0
-_TX1REG FAD 0 ABS 0
-_TX2REG F73 0 ABS 0
-_ANSELD F3B 0 ABS 0
-__Hbigbss 0 0 BIGRAM 1
-__Lbigbss 0 0 BIGRAM 1
-__Hintret 0 0 ABS 0
-__Lintret 0 0 ABS 0
-__Hramtop 600 0 RAM 0
-__Lramtop 600 0 RAM 0
-__Hstruct 0 0 COMRAM 1
-__Lstruct 0 0 COMRAM 1
-__Hbigdata 0 0 BIGRAM 1
-__Lbigdata 0 0 BIGRAM 1
-__Hmediumconst 0 0 MEDIUMCONST 0
-__Lmediumconst 0 0 MEDIUMCONST 0
-__Hfarbss 0 0 FARRAM 0
-__Lfarbss 0 0 FARRAM 0
-_keys_data 62 0 BANK0 1
-__Hintcode 2FA 0 CODE 0
-__Lintcode 2 0 CODE 0
-__Hfardata 0 0 FARRAM 0
-__Lfardata 0 0 FARRAM 0
-midi_note_on@velocity 34 0 COMRAM 1
-__pintcode 2 0 CODE 0
-__Habs1 0 0 ABS 0
-__Labs1 0 0 ABS 0
-__CFG_EBTR0$OFF 0 0 ABS 0
-__size_of_eusart2_putch 0 0 ABS 0
-__HnvFARRAM 0 0 FARRAM 0
-__LnvFARRAM 0 0 FARRAM 0
-__CFG_EBTR1$OFF 0 0 ABS 0
-__CFG_CCP2MX$PORTC1 0 0 ABS 0
-__end_of_eusart1_init 7D6E 0 CODE 0
-__CFG_EBTR2$OFF 0 0 ABS 0
-__CFG_CCP3MX$PORTB5 0 0 ABS 0
-__end_of_memset 7E00 0 CODE 0
-__Hdata 0 0 ABS 0
-__Ldata 0 0 ABS 0
-__CFG_EBTR3$OFF 0 0 ABS 0
-stackhi 0 0 ABS 0
-__HcstackBANK0 0 0 ABS 0
-__LcstackBANK0 0 0 ABS 0
-__pcstackBANK0 A2 0 BANK0 1
-__Htemp 36 0 COMRAM 1
-__Ltemp 35 0 COMRAM 1
-stacklo 0 0 ABS 0
-__Hrbit 0 0 COMRAM 1
-__Lrbit 0 0 COMRAM 1
-__Hinit 2FE 0 CODE 0
-__Linit 2FA 0 CODE 0
-__Hintcodelo 2FA 0 CODE 0
-__Lintcodelo 2FA 0 CODE 0
-_memset 7DD4 0 CODE 0
-__Hrbss 0 0 COMRAM 1
-__end_of_main 8000 0 CODE 0
-__Lrbss 0 0 COMRAM 1
-_isr$295 27 0 COMRAM 1
-__Htext 0 0 ABS 0
-__Ltext 0 0 ABS 0
-_isr$296 28 0 COMRAM 1
-__CFG_LVP$ON 0 0 ABS 0
-end_of_initialization 7D44 0 CODE 0
-_midi_set_status 7D8A 0 CODE 0
-_SPBRGH1 FB0 0 ABS 0
-_SPBRGH2 F76 0 ABS 0
-__size_of_init_hw 0 0 ABS 0
-__end_of_midi_set_channel 7DD4 0 CODE 0
-midi_note_on@channel 31 0 COMRAM 1
-_TRISCbits F94 0 ABS 0
-_TRISDbits F95 0 ABS 0
-_T2CONbits FBA 0 ABS 0
-_midi_set_channel 7DAE 0 CODE 0
-__size_of_eusart_write_midi 0 0 ABS 0
-__Hibigdata 0 0 CODE 0
-__Libigdata 0 0 CODE 0
-__Hifardata 0 0 CODE 0
-__Lifardata 0 0 CODE 0
-__Hbank0 0 0 ABS 0
-__Lbank0 0 0 ABS 0
-__Hbank1 0 0 ABS 0
-__Lbank1 0 0 ABS 0
-__Hbank2 0 0 ABS 0
-__Lbank2 0 0 ABS 0
-__Hbank3 0 0 ABS 0
-__Lbank3 0 0 ABS 0
-__Hbank4 0 0 ABS 0
-__Lbank4 0 0 ABS 0
-__Hbank5 0 0 ABS 0
-__Lbank5 0 0 ABS 0
-__Hpowerup 2FA 0 CODE 0
-__Lpowerup 2FA 0 CODE 0
-__Htext0 0 0 ABS 0
-__Ltext0 0 0 ABS 0
-_eusart_write_midi 7EB4 0 CODE 0
-__Htext1 0 0 ABS 0
-__Ltext1 0 0 ABS 0
-__ptext0 7F28 0 CODE 0
-__Htext2 0 0 ABS 0
-__Ltext2 0 0 ABS 0
-__ptext1 7E52 0 CODE 0
-__end_of_midi_note_on 7EB4 0 CODE 0
-__Htext3 0 0 ABS 0
-__Ltext3 0 0 ABS 0
-__ptext2 7D8A 0 CODE 0
-__Htext4 0 0 ABS 0
-__Ltext4 0 0 ABS 0
-__ptext3 7DAE 0 CODE 0
-__Htext5 0 0 ABS 0
-__CFG_P2BMX$PORTD2 0 0 ABS 0
-__Ltext5 0 0 ABS 0
-__ptext4 7DD4 0 CODE 0
-__Htext6 0 0 ABS 0
-__Ltext6 0 0 ABS 0
-__ptext5 7E00 0 CODE 0
-__Htext7 0 0 ABS 0
-__Ltext7 0 0 ABS 0
-__ptext6 7D6E 0 CODE 0
-__Htext8 0 0 ABS 0
-__Ltext8 0 0 ABS 0
-__ptext7 7D52 0 CODE 0
-__Htext9 0 0 ABS 0
-__Ltext9 0 0 ABS 0
-__ptext8 7EB4 0 CODE 0
-__CFG_T3CMX$PORTC0 0 0 ABS 0
-__ptext9 7D2C 0 CODE 0
-__Hclrtext 0 0 ABS 0
-__Lclrtext 0 0 ABS 0
-__CFG_HFOFST$ON 0 0 ABS 0
-_OSCTUNEbits F9B 0 ABS 0
-__end_of__initialization 7D44 0 CODE 0
-__CFG_PRICLKEN$ON 0 0 ABS 0
-memset@c 2C 0 COMRAM 1
-___rparam_used 1 0 ABS 0
-__size_of_memset 0 0 ABS 0
-memset@n 2E 0 COMRAM 1
-memset@p 30 0 COMRAM 1
-__Hidata 0 0 CODE 0
-__Lidata 0 0 CODE 0
-__Hrdata 0 0 COMRAM 1
-__Lrdata 0 0 COMRAM 1
-__Hidloc 0 0 IDLOC 0
-__Lidloc 0 0 IDLOC 0
-__CFG_PWRTEN$OFF 0 0 ABS 0
-__Hstack 0 0 STACK 2
-__Lstack 0 0 STACK 2
-_midi_note_on 7E52 0 CODE 0
-midi_set_channel@channel 2C 0 COMRAM 1
-__Hparam 0 0 ABS 0
-__Lparam 0 0 ABS 0
-__Hspace_0 8000 0 ABS 0
-__HcstackCOMRAM 0 0 ABS 0
-__Lspace_0 0 0 ABS 0
-__LcstackCOMRAM 0 0 ABS 0
-__end_of_isr 2FA 0 CODE 0
-__pcstackCOMRAM 1 0 COMRAM 1
-__Hspace_1 B0 0 ABS 0
-__Lspace_1 0 0 ABS 0
-__Hsmallconst 0 0 SMALLCONST 0
-__Lsmallconst 0 0 SMALLCONST 0
-eusart_write_midi@length 2F 0 COMRAM 1
-__Hspace_2 0 0 ABS 0
-__Lspace_2 0 0 ABS 0
-__Hnvbit 0 0 COMRAM 1
-__Lnvbit 0 0 COMRAM 1
-__Hcinit 0 0 ABS 0
-__Lcinit 0 0 ABS 0
-__pcinit 7D38 0 CODE 0
-__CFG_EBTRB$OFF 0 0 ABS 0
-_init_hw 7E00 0 CODE 0
-__ramtop 600 0 RAM 0
-__mediumconst 0 0 MEDIUMCONST 0
-__size_of_main 0 0 ABS 0
-__Hconst 0 0 CONST 0
-__Lconst 0 0 CONST 0
-__CFG_PLLCFG$ON 0 0 ABS 0
-__CFG_WRT0$OFF 0 0 ABS 0
-__CFG_WRT1$OFF 0 0 ABS 0
-midi_note_on@pkt 2F 0 COMRAM 1
-__HbssBANK0 0 0 ABS 0
-__LbssBANK0 0 0 ABS 0
-__CFG_MCLRE$EXTMCLR 0 0 ABS 0
-__CFG_WRT2$OFF 0 0 ABS 0
-__pbssBANK0 60 0 BANK0 1
-__CFG_WRT3$OFF 0 0 ABS 0
-__CFG_FCMEN$OFF 0 0 ABS 0
-__size_of_midi_set_status 0 0 ABS 0
-midi_note_on@note 33 0 COMRAM 1
-midi_set_status@pkt 2A 0 COMRAM 1
-_RCSTA1bits FAB 0 ABS 0
-_RCSTA2bits F71 0 ABS 0
-_TXSTA1bits FAC 0 ABS 0
-_TXSTA2bits F72 0 ABS 0
-___inthi_sp 0 0 STACK 2
-__size_of_midi_set_channel 0 0 ABS 0
-__CFG_WDTEN$OFF 0 0 ABS 0
-___intlo_sp 0 0 STACK 2
-_OSCCONbits FD3 0 ABS 0
-_INTCONbits FF2 0 ABS 0
-_keypresses 60 0 BANK0 1
-__CFG_CP0$OFF 0 0 ABS 0
-__smallconst 0 0 SMALLCONST 0
-main@message A9 0 BANK0 1
-__CFG_CP1$OFF 0 0 ABS 0
-memset@p1 2A 0 COMRAM 1
-__Hreset_vec 2 0 CODE 0
-__Lreset_vec 0 0 CODE 0
-__CFG_CP2$OFF 0 0 ABS 0
-__CFG_CP3$OFF 0 0 ABS 0
-__CFG_BORV$190 0 0 ABS 0
-__accesstop 60 0 ABS 0
-__end_of_midi_set_status 7DAE 0 CODE 0
-__Hintcode_body 0 0 ABS 0
-__Lintcode_body 0 0 ABS 0
-__CFG_PBADEN$ON 0 0 ABS 0
-intlevel0 0 0 CODE 0
-intlevel1 0 0 CODE 0
-__CFG_WRTB$OFF 0 0 ABS 0
-midi_set_status@status 2C 0 COMRAM 1
-intlevel2 0 0 CODE 0
-intlevel3 0 0 CODE 0
-__CFG_WRTC$OFF 0 0 ABS 0
-_BAUDCON1bits FB8 0 ABS 0
-__CFG_WRTD$OFF 0 0 ABS 0
-_BAUDCON2bits F70 0 ABS 0
-__CFG_CPB$OFF 0 0 ABS 0
-__CFG_CPD$OFF 0 0 ABS 0
-start_initialization 7D38 0 CODE 0
-__CFG_BOREN$SBORDIS 0 0 ABS 0
-__CFG_IESO$OFF 0 0 ABS 0
-_eusart1_init 7D52 0 CODE 0
-_eusart2_init 7D6E 0 CODE 0
-__end_of_eusart2_init 7D8A 0 CODE 0
-__initialization 7D38 0 CODE 0
-__activetblptr 2 0 ABS 0
-%segments
-reset_vec 0 2FD CODE 0 0
-cstackCOMRAM 1 35 COMRAM 1 1
-bssBANK0 60 AF BANK0 60 1
-text0 7F28 7FFF CODE 7F28 0
-text8 7EB4 7F27 CODE 7EB4 0
-text1 7E52 7EB3 CODE 7E52 0
-text5 7E00 7E51 CODE 7E00 0
-text4 7DD4 7DFF CODE 7DD4 0
-text3 7DAE 7DD3 CODE 7DAE 0
-text2 7D8A 7DAD CODE 7D8A 0
-text6 7D6E 7D89 CODE 7D6E 0
-text7 7D52 7D6D CODE 7D52 0
-cinit 7D38 7D51 CODE 7D38 0
-text9 7D2C 7D37 CODE 7D2C 0
-%locals
-dist/default/debug\src.debug.obj
-C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
-C:\Users\_prossn\AppData\Local\Temp\s5ls.
-1215 7D38 0 CODE 0
-1217 7D38 0 CODE 0
-1220 7D38 0 CODE 0
-1235 7D38 0 CODE 0
-1236 7D3C 0 CODE 0
-1237 7D3E 0 CODE 0
-1238 7D3E 0 CODE 0
-1239 7D40 0 CODE 0
-1240 7D42 0 CODE 0
-1246 7D44 0 CODE 0
-1248 7D44 0 CODE 0
-1249 7D46 0 CODE 0
-1251 7D48 0 CODE 0
-1252 7D4A 0 CODE 0
-1253 7D4C 0 CODE 0
-1254 7D4E 0 CODE 0
-main
\ No newline at end of file