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diff --git a/src/dist/default/debug/src.debug.lst b/src/dist/default/debug/src.debug.lst
new file mode 100644
index 0000000..e69de29
--- /dev/null
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diff --git a/src/dist/default/debug/src.debug.map b/src/dist/default/debug/src.debug.map
new file mode 100644
index 0000000..e69de29
--- /dev/null
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diff --git a/src/dist/default/debug/src.debug.obj b/src/dist/default/debug/src.debug.obj
new file mode 100644
index 0000000..e391aed
--- /dev/null
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diff --git a/src/dist/default/debug/src.debug.rlf b/src/dist/default/debug/src.debug.rlf
new file mode 100644
index 0000000..8586f2a
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new file mode 100644
index 0000000..cf91952
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diff --git a/src/dist/default/debug/src.debug.sym b/src/dist/default/debug/src.debug.sym
new file mode 100644
index 0000000..c440798
--- /dev/null
+++ b/src/dist/default/debug/src.debug.sym
@@ -0,0 +1,342 @@
+__end_of_eusart2_putch 7D38 0 CODE 0
+__CFG_XINST$OFF 0 0 ABS 0
+_PR2 FBB 0 ABS 0
+__S0 8000 0 ABS 0
+__S1 B0 0 ABS 0
+__Hintentry 0 0 ABS 0
+__Lintentry 0 0 ABS 0
+midi_set_channel@pkt 2A 0 COMRAM 1
+__end_of_init_hw 7E52 0 CODE 0
+_isr 2 0 CODE 0
+__end_of_eusart_write_midi 7F28 0 CODE 0
+_eusart2_putch 7D2C 0 CODE 0
+isr@i 29 0 COMRAM 1
+_main 7F28 0 CODE 0
+___sp 0 0 STACK 2
+btemp 35 0 COMRAM 1
+start 2FA 0 CODE 0
+__size_of_eusart1_init 0 0 ABS 0
+__size_of_eusart2_init 0 0 ABS 0
+eusart_write_midi@pkt 2B 0 COMRAM 1
+eusart2_putch@c 2A 0 COMRAM 1
+_RC1IF 7CF5 0 ABS 0
+_TX1IF 7CF4 0 ABS 0
+_TX2IF 7D24 0 ABS 0
+isr@data_a 25 0 COMRAM 1
+_TRISA F92 0 ABS 0
+_TRISB F93 0 ABS 0
+_PORTA F80 0 ABS 0
+_PORTB F81 0 ABS 0
+__Hirdata 0 0 CODE 0
+__Lirdata 0 0 CODE 0
+__HRAM 0 0 ABS 0
+__LRAM 1 0 ABS 0
+isr@data_b 26 0 COMRAM 1
+wtemp6 36 0 COMRAM 1
+__CFG_WDTPS$32768 0 0 ABS 0
+__Hconfig 0 0 CONFIG 0
+__Lconfig 0 0 CONFIG 0
+__CFG_FOSC$INTIO67 0 0 ABS 0
+main@i A7 0 BANK0 1
+__Hbigram 0 0 ABS 0
+__Lbigram 0 0 ABS 0
+__Hrparam 0 0 ABS 0
+__Lrparam 0 0 ABS 0
+__Hram 0 0 ABS 0
+__Lram 0 0 ABS 0
+__Hcomram 0 0 ABS 0
+__Lcomram 0 0 ABS 0
+__Hsfr 0 0 ABS 0
+__Lsfr 0 0 ABS 0
+__size_of_isr 0 0 ABS 0
+eusart_write_midi@data 31 0 COMRAM 1
+__Hbss 0 0 RAM 1
+__CFG_STVREN$ON 0 0 ABS 0
+__Lbss 0 0 RAM 1
+___param_bank 0 0 ABS 0
+__Hnvrram 0 0 COMRAM 1
+__Lnvrram 0 0 COMRAM 1
+int$flags 35 0 COMRAM 1
+__size_of_midi_note_on 0 0 ABS 0
+_SPBRG1 FAF 0 ABS 0
+_SPBRG2 F75 0 ABS 0
+_PIE1bits F9D 0 ABS 0
+__Heeprom_data 0 0 EEDATA 0
+__Leeprom_data 0 0 EEDATA 0
+_PIR1bits F9E 0 ABS 0
+__Hintsave_regs 0 0 BIGRAM 1
+__Lintsave_regs 0 0 BIGRAM 1
+_ANSELA F38 0 ABS 0
+_ANSELB F39 0 ABS 0
+_RC1REG FAE 0 ABS 0
+_ANSELC F3A 0 ABS 0
+_TX1REG FAD 0 ABS 0
+_TX2REG F73 0 ABS 0
+_ANSELD F3B 0 ABS 0
+__Hbigbss 0 0 BIGRAM 1
+__Lbigbss 0 0 BIGRAM 1
+__Hintret 0 0 ABS 0
+__Lintret 0 0 ABS 0
+__Hramtop 600 0 RAM 0
+__Lramtop 600 0 RAM 0
+__Hstruct 0 0 COMRAM 1
+__Lstruct 0 0 COMRAM 1
+__Hbigdata 0 0 BIGRAM 1
+__Lbigdata 0 0 BIGRAM 1
+__Hmediumconst 0 0 MEDIUMCONST 0
+__Lmediumconst 0 0 MEDIUMCONST 0
+__Hfarbss 0 0 FARRAM 0
+__Lfarbss 0 0 FARRAM 0
+_keys_data 62 0 BANK0 1
+__Hintcode 2FA 0 CODE 0
+__Lintcode 2 0 CODE 0
+__Hfardata 0 0 FARRAM 0
+__Lfardata 0 0 FARRAM 0
+midi_note_on@velocity 34 0 COMRAM 1
+__pintcode 2 0 CODE 0
+__Habs1 0 0 ABS 0
+__Labs1 0 0 ABS 0
+__CFG_EBTR0$OFF 0 0 ABS 0
+__size_of_eusart2_putch 0 0 ABS 0
+__HnvFARRAM 0 0 FARRAM 0
+__LnvFARRAM 0 0 FARRAM 0
+__CFG_EBTR1$OFF 0 0 ABS 0
+__CFG_CCP2MX$PORTC1 0 0 ABS 0
+__end_of_eusart1_init 7D6E 0 CODE 0
+__CFG_EBTR2$OFF 0 0 ABS 0
+__CFG_CCP3MX$PORTB5 0 0 ABS 0
+__end_of_memset 7E00 0 CODE 0
+__Hdata 0 0 ABS 0
+__Ldata 0 0 ABS 0
+__CFG_EBTR3$OFF 0 0 ABS 0
+stackhi 0 0 ABS 0
+__HcstackBANK0 0 0 ABS 0
+__LcstackBANK0 0 0 ABS 0
+__pcstackBANK0 A2 0 BANK0 1
+__Htemp 36 0 COMRAM 1
+__Ltemp 35 0 COMRAM 1
+stacklo 0 0 ABS 0
+__Hrbit 0 0 COMRAM 1
+__Lrbit 0 0 COMRAM 1
+__Hinit 2FE 0 CODE 0
+__Linit 2FA 0 CODE 0
+__Hintcodelo 2FA 0 CODE 0
+__Lintcodelo 2FA 0 CODE 0
+_memset 7DD4 0 CODE 0
+__Hrbss 0 0 COMRAM 1
+__end_of_main 8000 0 CODE 0
+__Lrbss 0 0 COMRAM 1
+_isr$295 27 0 COMRAM 1
+__Htext 0 0 ABS 0
+__Ltext 0 0 ABS 0
+_isr$296 28 0 COMRAM 1
+__CFG_LVP$ON 0 0 ABS 0
+end_of_initialization 7D44 0 CODE 0
+_midi_set_status 7D8A 0 CODE 0
+_SPBRGH1 FB0 0 ABS 0
+_SPBRGH2 F76 0 ABS 0
+__size_of_init_hw 0 0 ABS 0
+__end_of_midi_set_channel 7DD4 0 CODE 0
+midi_note_on@channel 31 0 COMRAM 1
+_TRISCbits F94 0 ABS 0
+_TRISDbits F95 0 ABS 0
+_T2CONbits FBA 0 ABS 0
+_midi_set_channel 7DAE 0 CODE 0
+__size_of_eusart_write_midi 0 0 ABS 0
+__Hibigdata 0 0 CODE 0
+__Libigdata 0 0 CODE 0
+__Hifardata 0 0 CODE 0
+__Lifardata 0 0 CODE 0
+__Hbank0 0 0 ABS 0
+__Lbank0 0 0 ABS 0
+__Hbank1 0 0 ABS 0
+__Lbank1 0 0 ABS 0
+__Hbank2 0 0 ABS 0
+__Lbank2 0 0 ABS 0
+__Hbank3 0 0 ABS 0
+__Lbank3 0 0 ABS 0
+__Hbank4 0 0 ABS 0
+__Lbank4 0 0 ABS 0
+__Hbank5 0 0 ABS 0
+__Lbank5 0 0 ABS 0
+__Hpowerup 2FA 0 CODE 0
+__Lpowerup 2FA 0 CODE 0
+__Htext0 0 0 ABS 0
+__Ltext0 0 0 ABS 0
+_eusart_write_midi 7EB4 0 CODE 0
+__Htext1 0 0 ABS 0
+__Ltext1 0 0 ABS 0
+__ptext0 7F28 0 CODE 0
+__Htext2 0 0 ABS 0
+__Ltext2 0 0 ABS 0
+__ptext1 7E52 0 CODE 0
+__end_of_midi_note_on 7EB4 0 CODE 0
+__Htext3 0 0 ABS 0
+__Ltext3 0 0 ABS 0
+__ptext2 7D8A 0 CODE 0
+__Htext4 0 0 ABS 0
+__Ltext4 0 0 ABS 0
+__ptext3 7DAE 0 CODE 0
+__Htext5 0 0 ABS 0
+__CFG_P2BMX$PORTD2 0 0 ABS 0
+__Ltext5 0 0 ABS 0
+__ptext4 7DD4 0 CODE 0
+__Htext6 0 0 ABS 0
+__Ltext6 0 0 ABS 0
+__ptext5 7E00 0 CODE 0
+__Htext7 0 0 ABS 0
+__Ltext7 0 0 ABS 0
+__ptext6 7D6E 0 CODE 0
+__Htext8 0 0 ABS 0
+__Ltext8 0 0 ABS 0
+__ptext7 7D52 0 CODE 0
+__Htext9 0 0 ABS 0
+__Ltext9 0 0 ABS 0
+__ptext8 7EB4 0 CODE 0
+__CFG_T3CMX$PORTC0 0 0 ABS 0
+__ptext9 7D2C 0 CODE 0
+__Hclrtext 0 0 ABS 0
+__Lclrtext 0 0 ABS 0
+__CFG_HFOFST$ON 0 0 ABS 0
+_OSCTUNEbits F9B 0 ABS 0
+__end_of__initialization 7D44 0 CODE 0
+__CFG_PRICLKEN$ON 0 0 ABS 0
+memset@c 2C 0 COMRAM 1
+___rparam_used 1 0 ABS 0
+__size_of_memset 0 0 ABS 0
+memset@n 2E 0 COMRAM 1
+memset@p 30 0 COMRAM 1
+__Hidata 0 0 CODE 0
+__Lidata 0 0 CODE 0
+__Hrdata 0 0 COMRAM 1
+__Lrdata 0 0 COMRAM 1
+__Hidloc 0 0 IDLOC 0
+__Lidloc 0 0 IDLOC 0
+__CFG_PWRTEN$OFF 0 0 ABS 0
+__Hstack 0 0 STACK 2
+__Lstack 0 0 STACK 2
+_midi_note_on 7E52 0 CODE 0
+midi_set_channel@channel 2C 0 COMRAM 1
+__Hparam 0 0 ABS 0
+__Lparam 0 0 ABS 0
+__Hspace_0 8000 0 ABS 0
+__HcstackCOMRAM 0 0 ABS 0
+__Lspace_0 0 0 ABS 0
+__LcstackCOMRAM 0 0 ABS 0
+__end_of_isr 2FA 0 CODE 0
+__pcstackCOMRAM 1 0 COMRAM 1
+__Hspace_1 B0 0 ABS 0
+__Lspace_1 0 0 ABS 0
+__Hsmallconst 0 0 SMALLCONST 0
+__Lsmallconst 0 0 SMALLCONST 0
+eusart_write_midi@length 2F 0 COMRAM 1
+__Hspace_2 0 0 ABS 0
+__Lspace_2 0 0 ABS 0
+__Hnvbit 0 0 COMRAM 1
+__Lnvbit 0 0 COMRAM 1
+__Hcinit 0 0 ABS 0
+__Lcinit 0 0 ABS 0
+__pcinit 7D38 0 CODE 0
+__CFG_EBTRB$OFF 0 0 ABS 0
+_init_hw 7E00 0 CODE 0
+__ramtop 600 0 RAM 0
+__mediumconst 0 0 MEDIUMCONST 0
+__size_of_main 0 0 ABS 0
+__Hconst 0 0 CONST 0
+__Lconst 0 0 CONST 0
+__CFG_PLLCFG$ON 0 0 ABS 0
+__CFG_WRT0$OFF 0 0 ABS 0
+__CFG_WRT1$OFF 0 0 ABS 0
+midi_note_on@pkt 2F 0 COMRAM 1
+__HbssBANK0 0 0 ABS 0
+__LbssBANK0 0 0 ABS 0
+__CFG_MCLRE$EXTMCLR 0 0 ABS 0
+__CFG_WRT2$OFF 0 0 ABS 0
+__pbssBANK0 60 0 BANK0 1
+__CFG_WRT3$OFF 0 0 ABS 0
+__CFG_FCMEN$OFF 0 0 ABS 0
+__size_of_midi_set_status 0 0 ABS 0
+midi_note_on@note 33 0 COMRAM 1
+midi_set_status@pkt 2A 0 COMRAM 1
+_RCSTA1bits FAB 0 ABS 0
+_RCSTA2bits F71 0 ABS 0
+_TXSTA1bits FAC 0 ABS 0
+_TXSTA2bits F72 0 ABS 0
+___inthi_sp 0 0 STACK 2
+__size_of_midi_set_channel 0 0 ABS 0
+__CFG_WDTEN$OFF 0 0 ABS 0
+___intlo_sp 0 0 STACK 2
+_OSCCONbits FD3 0 ABS 0
+_INTCONbits FF2 0 ABS 0
+_keypresses 60 0 BANK0 1
+__CFG_CP0$OFF 0 0 ABS 0
+__smallconst 0 0 SMALLCONST 0
+main@message A9 0 BANK0 1
+__CFG_CP1$OFF 0 0 ABS 0
+memset@p1 2A 0 COMRAM 1
+__Hreset_vec 2 0 CODE 0
+__Lreset_vec 0 0 CODE 0
+__CFG_CP2$OFF 0 0 ABS 0
+__CFG_CP3$OFF 0 0 ABS 0
+__CFG_BORV$190 0 0 ABS 0
+__accesstop 60 0 ABS 0
+__end_of_midi_set_status 7DAE 0 CODE 0
+__Hintcode_body 0 0 ABS 0
+__Lintcode_body 0 0 ABS 0
+__CFG_PBADEN$ON 0 0 ABS 0
+intlevel0 0 0 CODE 0
+intlevel1 0 0 CODE 0
+__CFG_WRTB$OFF 0 0 ABS 0
+midi_set_status@status 2C 0 COMRAM 1
+intlevel2 0 0 CODE 0
+intlevel3 0 0 CODE 0
+__CFG_WRTC$OFF 0 0 ABS 0
+_BAUDCON1bits FB8 0 ABS 0
+__CFG_WRTD$OFF 0 0 ABS 0
+_BAUDCON2bits F70 0 ABS 0
+__CFG_CPB$OFF 0 0 ABS 0
+__CFG_CPD$OFF 0 0 ABS 0
+start_initialization 7D38 0 CODE 0
+__CFG_BOREN$SBORDIS 0 0 ABS 0
+__CFG_IESO$OFF 0 0 ABS 0
+_eusart1_init 7D52 0 CODE 0
+_eusart2_init 7D6E 0 CODE 0
+__end_of_eusart2_init 7D8A 0 CODE 0
+__initialization 7D38 0 CODE 0
+__activetblptr 2 0 ABS 0
+%segments
+reset_vec 0 2FD CODE 0 0
+cstackCOMRAM 1 35 COMRAM 1 1
+bssBANK0 60 AF BANK0 60 1
+text0 7F28 7FFF CODE 7F28 0
+text8 7EB4 7F27 CODE 7EB4 0
+text1 7E52 7EB3 CODE 7E52 0
+text5 7E00 7E51 CODE 7E00 0
+text4 7DD4 7DFF CODE 7DD4 0
+text3 7DAE 7DD3 CODE 7DAE 0
+text2 7D8A 7DAD CODE 7D8A 0
+text6 7D6E 7D89 CODE 7D6E 0
+text7 7D52 7D6D CODE 7D52 0
+cinit 7D38 7D51 CODE 7D38 0
+text9 7D2C 7D37 CODE 7D2C 0
+%locals
+dist/default/debug\src.debug.obj
+C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
+C:\Users\_prossn\AppData\Local\Temp\s5ls.
+1215 7D38 0 CODE 0
+1217 7D38 0 CODE 0
+1220 7D38 0 CODE 0
+1235 7D38 0 CODE 0
+1236 7D3C 0 CODE 0
+1237 7D3E 0 CODE 0
+1238 7D3E 0 CODE 0
+1239 7D40 0 CODE 0
+1240 7D42 0 CODE 0
+1246 7D44 0 CODE 0
+1248 7D44 0 CODE 0
+1249 7D46 0 CODE 0
+1251 7D48 0 CODE 0
+1252 7D4A 0 CODE 0
+1253 7D4C 0 CODE 0
+1254 7D4E 0 CODE 0
+main
+\ No newline at end of file