From 0a9c19f83f6a08f18871c9728c8cc474a615a3be Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Tue, 27 Feb 2018 10:38:17 +0100
Subject: MPLab X garbage

---
 src/dist/default/production/src.production.sdb | 296 +++++++++++++++----------
 1 file changed, 185 insertions(+), 111 deletions(-)

(limited to 'src/dist/default/production/src.production.sdb')

diff --git a/src/dist/default/production/src.production.sdb b/src/dist/default/production/src.production.sdb
index f9bbdf0..c0c1673 100644
--- a/src/dist/default/production/src.production.sdb
+++ b/src/dist/default/production/src.production.sdb
@@ -3,8 +3,8 @@
 [d edition pro ]
 [d chip 18F45K22 ]
 [d frameptr 4065 ]
-"216 Z:\SAMB_4\projects\xilofono\src\main.c
-[e E41 . `uc
+"232 Z:\SAMB_4\projects\xilofono\src\main.c
+[e E43 . `uc
 C 0
 D 1
 E 2
@@ -55,13 +55,13 @@ B 6
 [v ___flmul __flmul `(d  1 e 3 0 ]
 "15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c
 [v ___lmul __lmul `(ul  1 e 4 0 ]
-"101 Z:\SAMB_4\projects\xilofono\src\main.c
+"113 Z:\SAMB_4\projects\xilofono\src\main.c
 [v _isr isr `II(v  1 e 1 0 ]
-"140
+"150
 [v _init_hw init_hw `T(v  1 e 1 0 ]
-"204
+"215
 [v _main main `(v  1 e 1 0 ]
-"226
+"261
 [v _eusart_write_midi eusart_write_midi `(i  1 e 2 0 ]
 "40 Z:\SAMB_4\projects\xilofono\src\midi.c
 [v _midi_set_status midi_set_status `(i  1 e 2 0 ]
@@ -71,10 +71,14 @@ B 6
 [v _midi_note_on midi_note_on `(i  1 e 2 0 ]
 "4 Z:\SAMB_4\projects\xilofono\src\rs232.c
 [v _eusart1_init eusart1_init `(v  1 e 1 0 ]
-"29
-[v _putch putch `(v  1 e 1 0 ]
-"35
-[v _getch getch `(uc  1 e 1 0 ]
+"25
+[v _eusart2_init eusart2_init `(v  1 e 1 0 ]
+"46
+[v _eusart1_putch eusart1_putch `(v  1 e 1 0 ]
+"52
+[v _eusart2_putch eusart2_putch `(v  1 e 1 0 ]
+"58
+[v _eusart1_getch eusart1_getch `(uc  1 e 1 0 ]
 "50 C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
 [v _ANSELA ANSELA `VEuc  1 e 1 @3896 ]
 "95
@@ -83,6 +87,97 @@ B 6
 [v _ANSELC ANSELC `VEuc  1 e 1 @3898 ]
 "196
 [v _ANSELD ANSELD `VEuc  1 e 1 @3899 ]
+[s S784 . 1 `uc 1 ABDEN 1 0 :1:0 
+`uc 1 WUE 1 0 :1:1 
+`uc 1 . 1 0 :1:2 
+`uc 1 BRG16 1 0 :1:3 
+`uc 1 CKTXP 1 0 :1:4 
+`uc 1 DTRXP 1 0 :1:5 
+`uc 1 RCIDL 1 0 :1:6 
+`uc 1 ABDOVF 1 0 :1:7 
+]
+"4328
+[s S793 . 1 `uc 1 . 1 0 :4:0 
+`uc 1 SCKP 1 0 :1:4 
+]
+[s S1033 . 1 `uc 1 ABDEN2 1 0 :1:0 
+`uc 1 WUE2 1 0 :1:1 
+`uc 1 . 1 0 :1:2 
+`uc 1 BRG162 1 0 :1:3 
+`uc 1 SCKP2 1 0 :1:4 
+`uc 1 DTRXP2 1 0 :1:5 
+`uc 1 RCIDL2 1 0 :1:6 
+`uc 1 ABDOVF2 1 0 :1:7 
+]
+[s S1042 . 1 `uc 1 . 1 0 :4:0 
+`uc 1 TXCKP2 1 0 :1:4 
+`uc 1 RXDTP2 1 0 :1:5 
+`uc 1 RCMT2 1 0 :1:6 
+]
+[u S1047 . 1 `S784 1 . 1 0 `S793 1 . 1 0 `S1033 1 . 1 0 `S1042 1 . 1 0 ]
+[v _BAUDCON2bits BAUDCON2bits `VES1047  1 e 1 @3952 ]
+[s S712 . 1 `uc 1 RX9D 1 0 :1:0 
+`uc 1 OERR 1 0 :1:1 
+`uc 1 FERR 1 0 :1:2 
+`uc 1 ADDEN 1 0 :1:3 
+`uc 1 CREN 1 0 :1:4 
+`uc 1 SREN 1 0 :1:5 
+`uc 1 RX9 1 0 :1:6 
+`uc 1 SPEN 1 0 :1:7 
+]
+"4593
+[s S721 . 1 `uc 1 . 1 0 :3:0 
+`uc 1 ADEN 1 0 :1:3 
+]
+[s S968 . 1 `uc 1 RX9D2 1 0 :1:0 
+`uc 1 OERR2 1 0 :1:1 
+`uc 1 FERR2 1 0 :1:2 
+`uc 1 ADDEN2 1 0 :1:3 
+`uc 1 CREN2 1 0 :1:4 
+`uc 1 SREN2 1 0 :1:5 
+`uc 1 RX92 1 0 :1:6 
+`uc 1 SPEN2 1 0 :1:7 
+]
+[s S977 . 1 `uc 1 RCD82 1 0 :1:0 
+`uc 1 . 1 0 :5:1 
+`uc 1 RC8_92 1 0 :1:6 
+]
+[s S981 . 1 `uc 1 . 1 0 :6:0 
+`uc 1 RC92 1 0 :1:6 
+]
+[u S984 . 1 `S712 1 . 1 0 `S721 1 . 1 0 `S968 1 . 1 0 `S977 1 . 1 0 `S981 1 . 1 0 ]
+[v _RCSTA2bits RCSTA2bits `VES984  1 e 1 @3953 ]
+[s S663 . 1 `uc 1 TX9D 1 0 :1:0 
+`uc 1 TRMT 1 0 :1:1 
+`uc 1 BRGH 1 0 :1:2 
+`uc 1 SENDB 1 0 :1:3 
+`uc 1 SYNC 1 0 :1:4 
+`uc 1 TXEN 1 0 :1:5 
+`uc 1 TX9 1 0 :1:6 
+`uc 1 CSRC 1 0 :1:7 
+]
+"4873
+[s S916 . 1 `uc 1 TX9D2 1 0 :1:0 
+`uc 1 TRMT2 1 0 :1:1 
+`uc 1 BRGH2 1 0 :1:2 
+`uc 1 SENDB2 1 0 :1:3 
+`uc 1 SYNC2 1 0 :1:4 
+`uc 1 TXEN2 1 0 :1:5 
+`uc 1 TX92 1 0 :1:6 
+`uc 1 CSRC2 1 0 :1:7 
+]
+[s S925 . 1 `uc 1 TXD82 1 0 :1:0 
+`uc 1 . 1 0 :5:1 
+`uc 1 TX8_92 1 0 :1:6 
+]
+[u S929 . 1 `S663 1 . 1 0 `S916 1 . 1 0 `S925 1 . 1 0 ]
+[v _TXSTA2bits TXSTA2bits `VES929  1 e 1 @3954 ]
+"5093
+[v _TX2REG TX2REG `VEuc  1 e 1 @3955 ]
+"5164
+[v _SPBRG2 SPBRG2 `VEuc  1 e 1 @3957 ]
+"5202
+[v _SPBRGH2 SPBRGH2 `VEuc  1 e 1 @3958 ]
 "6278
 [v _PORTA PORTA `VEuc  1 e 1 @3968 ]
 [s S160 . 1 `uc 1 RA0 1 0 :1:0 
@@ -211,7 +306,7 @@ B 6
 [v _TRISA TRISA `VEuc  1 e 1 @3986 ]
 "8280
 [v _TRISB TRISB `VEuc  1 e 1 @3987 ]
-[s S855 . 1 `uc 1 TRISC0 1 0 :1:0 
+[s S867 . 1 `uc 1 TRISC0 1 0 :1:0 
 `uc 1 TRISC1 1 0 :1:1 
 `uc 1 TRISC2 1 0 :1:2 
 `uc 1 TRISC3 1 0 :1:3 
@@ -221,7 +316,7 @@ B 6
 `uc 1 TRISC7 1 0 :1:7 
 ]
 "8534
-[s S864 . 1 `uc 1 RC0 1 0 :1:0 
+[s S876 . 1 `uc 1 RC0 1 0 :1:0 
 `uc 1 RC1 1 0 :1:1 
 `uc 1 RC2 1 0 :1:2 
 `uc 1 RC3 1 0 :1:3 
@@ -230,8 +325,8 @@ B 6
 `uc 1 RC6 1 0 :1:6 
 `uc 1 RC7 1 0 :1:7 
 ]
-[u S873 . 1 `S855 1 . 1 0 `S864 1 . 1 0 ]
-[v _TRISCbits TRISCbits `VES873  1 e 1 @3988 ]
+[u S885 . 1 `S867 1 . 1 0 `S876 1 . 1 0 ]
+[v _TRISCbits TRISCbits `VES885  1 e 1 @3988 ]
 [s S418 . 1 `uc 1 TRISD0 1 0 :1:0 
 `uc 1 TRISD1 1 0 :1:1 
 `uc 1 TRISD2 1 0 :1:2 
@@ -290,20 +385,8 @@ B 6
 ]
 [u S141 . 1 `S128 1 . 1 0 `S136 1 . 1 0 ]
 [v _PIR1bits PIR1bits `VES141  1 e 1 @3998 ]
-[s S700 . 1 `uc 1 RX9D 1 0 :1:0 
-`uc 1 OERR 1 0 :1:1 
-`uc 1 FERR 1 0 :1:2 
-`uc 1 ADDEN 1 0 :1:3 
-`uc 1 CREN 1 0 :1:4 
-`uc 1 SREN 1 0 :1:5 
-`uc 1 RX9 1 0 :1:6 
-`uc 1 SPEN 1 0 :1:7 
-]
 "10396
-[s S709 . 1 `uc 1 . 1 0 :3:0 
-`uc 1 ADEN 1 0 :1:3 
-]
-[s S712 . 1 `uc 1 RX9D1 1 0 :1:0 
+[s S724 . 1 `uc 1 RX9D1 1 0 :1:0 
 `uc 1 OERR1 1 0 :1:1 
 `uc 1 FERR1 1 0 :1:2 
 `uc 1 ADDEN1 1 0 :1:3 
@@ -312,29 +395,20 @@ B 6
 `uc 1 RX91 1 0 :1:6 
 `uc 1 SPEN1 1 0 :1:7 
 ]
-[s S721 . 1 `uc 1 RCD8 1 0 :1:0 
+[s S733 . 1 `uc 1 RCD8 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 RC8_9 1 0 :1:6 
 ]
-[s S725 . 1 `uc 1 . 1 0 :6:0 
+[s S737 . 1 `uc 1 . 1 0 :6:0 
 `uc 1 RC9 1 0 :1:6 
 ]
-[s S728 . 1 `uc 1 . 1 0 :5:0 
+[s S740 . 1 `uc 1 . 1 0 :5:0 
 `uc 1 SRENA 1 0 :1:5 
 ]
-[u S731 . 1 `S700 1 . 1 0 `S709 1 . 1 0 `S712 1 . 1 0 `S721 1 . 1 0 `S725 1 . 1 0 `S728 1 . 1 0 ]
-[v _RCSTA1bits RCSTA1bits `VES731  1 e 1 @4011 ]
-[s S651 . 1 `uc 1 TX9D 1 0 :1:0 
-`uc 1 TRMT 1 0 :1:1 
-`uc 1 BRGH 1 0 :1:2 
-`uc 1 SENDB 1 0 :1:3 
-`uc 1 SYNC 1 0 :1:4 
-`uc 1 TXEN 1 0 :1:5 
-`uc 1 TX9 1 0 :1:6 
-`uc 1 CSRC 1 0 :1:7 
-]
+[u S743 . 1 `S712 1 . 1 0 `S721 1 . 1 0 `S724 1 . 1 0 `S733 1 . 1 0 `S737 1 . 1 0 `S740 1 . 1 0 ]
+[v _RCSTA1bits RCSTA1bits `VES743  1 e 1 @4011 ]
 "10840
-[s S660 . 1 `uc 1 TX9D1 1 0 :1:0 
+[s S672 . 1 `uc 1 TX9D1 1 0 :1:0 
 `uc 1 TRMT1 1 0 :1:1 
 `uc 1 BRGH1 1 0 :1:2 
 `uc 1 SENDB1 1 0 :1:3 
@@ -343,12 +417,12 @@ B 6
 `uc 1 TX91 1 0 :1:6 
 `uc 1 CSRC1 1 0 :1:7 
 ]
-[s S669 . 1 `uc 1 TXD8 1 0 :1:0 
+[s S681 . 1 `uc 1 TXD8 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 TX8_9 1 0 :1:6 
 ]
-[u S673 . 1 `S651 1 . 1 0 `S660 1 . 1 0 `S669 1 . 1 0 ]
-[v _TXSTA1bits TXSTA1bits `VES673  1 e 1 @4012 ]
+[u S685 . 1 `S663 1 . 1 0 `S672 1 . 1 0 `S681 1 . 1 0 ]
+[v _TXSTA1bits TXSTA1bits `VES685  1 e 1 @4012 ]
 "11183
 [v _TX1REG TX1REG `VEuc  1 e 1 @4013 ]
 "11261
@@ -357,20 +431,8 @@ B 6
 [v _SPBRG1 SPBRG1 `VEuc  1 e 1 @4015 ]
 "11408
 [v _SPBRGH1 SPBRGH1 `VEuc  1 e 1 @4016 ]
-[s S772 . 1 `uc 1 ABDEN 1 0 :1:0 
-`uc 1 WUE 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 BRG16 1 0 :1:3 
-`uc 1 CKTXP 1 0 :1:4 
-`uc 1 DTRXP 1 0 :1:5 
-`uc 1 RCIDL 1 0 :1:6 
-`uc 1 ABDOVF 1 0 :1:7 
-]
 "12436
-[s S781 . 1 `uc 1 . 1 0 :4:0 
-`uc 1 SCKP 1 0 :1:4 
-]
-[s S784 . 1 `uc 1 ABDEN1 1 0 :1:0 
+[s S796 . 1 `uc 1 ABDEN1 1 0 :1:0 
 `uc 1 WUE1 1 0 :1:1 
 `uc 1 . 1 0 :1:2 
 `uc 1 BRG161 1 0 :1:3 
@@ -379,24 +441,24 @@ B 6
 `uc 1 RCIDL1 1 0 :1:6 
 `uc 1 ABDOVF1 1 0 :1:7 
 ]
-[s S793 . 1 `uc 1 . 1 0 :4:0 
+[s S805 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 TXCKP 1 0 :1:4 
 `uc 1 RXDTP 1 0 :1:5 
 `uc 1 RCMT 1 0 :1:6 
 ]
-[s S798 . 1 `uc 1 . 1 0 :4:0 
+[s S810 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 TXCKP1 1 0 :1:4 
 `uc 1 RXDTP1 1 0 :1:5 
 `uc 1 RCMT1 1 0 :1:6 
 ]
-[s S803 . 1 `uc 1 . 1 0 :5:0 
+[s S815 . 1 `uc 1 . 1 0 :5:0 
 `uc 1 RXCKP 1 0 :1:5 
 ]
-[s S806 . 1 `uc 1 . 1 0 :1:0 
+[s S818 . 1 `uc 1 . 1 0 :1:0 
 `uc 1 W4E 1 0 :1:1 
 ]
-[u S809 . 1 `S772 1 . 1 0 `S781 1 . 1 0 `S784 1 . 1 0 `S793 1 . 1 0 `S798 1 . 1 0 `S803 1 . 1 0 `S806 1 . 1 0 ]
-[v _BAUDCON1bits BAUDCON1bits `VES809  1 e 1 @4024 ]
+[u S821 . 1 `S784 1 . 1 0 `S793 1 . 1 0 `S796 1 . 1 0 `S805 1 . 1 0 `S810 1 . 1 0 `S815 1 . 1 0 `S818 1 . 1 0 ]
+[v _BAUDCON1bits BAUDCON1bits `VES821  1 e 1 @4024 ]
 [s S459 . 1 `uc 1 T2CKPS 1 0 :2:0 
 `uc 1 TMR2ON 1 0 :1:2 
 `uc 1 T2OUTPS 1 0 :4:3 
@@ -460,98 +522,110 @@ B 6
 [v _RC1IF RC1IF `VEb  1 e 0 @31989 ]
 "19488
 [v _TX1IF TX1IF `VEb  1 e 0 @31988 ]
-"95 Z:\SAMB_4\projects\xilofono\src\main.c
-[v _keypresses keypresses `VE[15]ui  1 e 30 0 ]
-"204
+"19496
+[v _TX2IF TX2IF `VEb  1 e 0 @32036 ]
+"105 Z:\SAMB_4\projects\xilofono\src\main.c
+[v _keys_data keys_data `VE[16]ul  1 e 64 0 ]
+"107
+[v _keypresses keypresses `VEui  1 e 2 0 ]
+"215
 [v _main main `(v  1 e 1 0 ]
 {
-[s S521 . 7 `uc 1 status 1 0 :4:0 
+[s S525 . 7 `uc 1 status 1 0 :4:0 
 `uc 1 channel 1 0 :4:4 
 `ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"207
-[v main@sample_message sample_message `S521  1 a 7 2 ]
-"223
+"218
+[v main@message message `S525  1 a 7 13 ]
+"217
+[v main@i i `ui  1 a 2 11 ]
+"258
 } 0
 "62 Z:\SAMB_4\projects\xilofono\src\midi.c
 [v _midi_note_on midi_note_on `(i  1 e 2 0 ]
 {
-[s S521 . 7 `uc 1 status 1 0 :4:0 
+[s S525 . 7 `uc 1 status 1 0 :4:0 
 `uc 1 channel 1 0 :4:4 
 `ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_note_on@pkt pkt `*.39S521  1 p 2 30 ]
-[v midi_note_on@channel channel `ui  1 p 2 32 ]
-[v midi_note_on@note note `E31  1 p 1 34 ]
-[v midi_note_on@velocity velocity `uc  1 p 1 35 ]
-"83
+[v midi_note_on@pkt pkt `*.39S525  1 p 2 0 ]
+[v midi_note_on@channel channel `ui  1 p 2 2 ]
+[v midi_note_on@note note `E31  1 p 1 4 ]
+[v midi_note_on@velocity velocity `uc  1 p 1 5 ]
+"85
 } 0
 "40
 [v _midi_set_status midi_set_status `(i  1 e 2 0 ]
 {
-[s S521 . 7 `uc 1 status 1 0 :4:0 
+[s S525 . 7 `uc 1 status 1 0 :4:0 
 `uc 1 channel 1 0 :4:4 
 `ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_status@pkt pkt `*.39S521  1 p 2 25 ]
-[v midi_set_status@status status `E40  1 p 1 27 ]
+[v midi_set_status@pkt pkt `*.39S525  1 p 2 42 ]
+[v midi_set_status@status status `E40  1 p 1 44 ]
 "49
 } 0
 "51
 [v _midi_set_channel midi_set_channel `(i  1 e 2 0 ]
 {
-[s S521 . 7 `uc 1 status 1 0 :4:0 
+[s S525 . 7 `uc 1 status 1 0 :4:0 
 `uc 1 channel 1 0 :4:4 
 `ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-[v midi_set_channel@pkt pkt `*.39S521  1 p 2 25 ]
-[v midi_set_channel@channel channel `ui  1 p 2 27 ]
+[v midi_set_channel@pkt pkt `*.39S525  1 p 2 42 ]
+[v midi_set_channel@channel channel `ui  1 p 2 44 ]
 "60
 } 0
 "8 C:\Program Files\Microchip\xc8\v1.44\sources\common\memset.c
 [v _memset memset `(*.39v  1 e 2 0 ]
 {
 "15
-[v memset@p p `*.39uc  1 a 2 31 ]
+[v memset@p p `*.39uc  1 a 2 48 ]
 "8
-[v memset@p1 p1 `*.39v  1 p 2 25 ]
-[v memset@c c `i  1 p 2 27 ]
-[v memset@n n `ui  1 p 2 29 ]
+[v memset@p1 p1 `*.39v  1 p 2 42 ]
+[v memset@c c `i  1 p 2 44 ]
+[v memset@n n `ui  1 p 2 46 ]
 "22
 } 0
-"140 Z:\SAMB_4\projects\xilofono\src\main.c
+"150 Z:\SAMB_4\projects\xilofono\src\main.c
 [v _init_hw init_hw `T(v  1 e 1 0 ]
 {
-"200
+"211
 } 0
-"4 Z:\SAMB_4\projects\xilofono\src\rs232.c
+"25 Z:\SAMB_4\projects\xilofono\src\rs232.c
+[v _eusart2_init eusart2_init `(v  1 e 1 0 ]
+{
+"44
+} 0
+"4
 [v _eusart1_init eusart1_init `(v  1 e 1 0 ]
 {
-"22
+"23
 } 0
-"226 Z:\SAMB_4\projects\xilofono\src\main.c
+"261 Z:\SAMB_4\projects\xilofono\src\main.c
 [v _eusart_write_midi eusart_write_midi `(i  1 e 2 0 ]
 {
-"229
-[v eusart_write_midi@data data `*.39uc  1 a 2 32 ]
-"228
-[v eusart_write_midi@length length `ui  1 a 2 30 ]
-[s S521 . 7 `uc 1 status 1 0 :4:0 
+"264
+[v eusart_write_midi@data data `*.39uc  1 a 2 49 ]
+"263
+[v eusart_write_midi@length length `ui  1 a 2 47 ]
+[s S525 . 7 `uc 1 status 1 0 :4:0 
 `uc 1 channel 1 0 :4:4 
 `ui 1 data_size 2 1 `[4]uc 1 data 4 3 ]
-"226
-[v eusart_write_midi@pkt pkt `*.39CS521  1 p 2 26 ]
-"245
+"261
+[v eusart_write_midi@pkt pkt `*.39CS525  1 p 2 43 ]
+"280
 } 0
-"29 Z:\SAMB_4\projects\xilofono\src\rs232.c
-[v _putch putch `(v  1 e 1 0 ]
+"52 Z:\SAMB_4\projects\xilofono\src\rs232.c
+[v _eusart2_putch eusart2_putch `(v  1 e 1 0 ]
 {
-[v putch@c c `uc  1 a 1 wreg ]
-[v putch@c c `uc  1 a 1 wreg ]
-[v putch@c c `uc  1 a 1 25 ]
-"33
+[v eusart2_putch@c c `uc  1 a 1 wreg ]
+[v eusart2_putch@c c `uc  1 a 1 wreg ]
+[v eusart2_putch@c c `uc  1 a 1 42 ]
+"56
 } 0
-"101 Z:\SAMB_4\projects\xilofono\src\main.c
+"113 Z:\SAMB_4\projects\xilofono\src\main.c
 [v _isr isr `II(v  1 e 1 0 ]
 {
-"103
-[v isr@i i `uc  1 a 1 24 ]
-[v isr@data data `uc  1 a 1 23 ]
-"137
+"115
+[v isr@i i `uc  1 a 1 41 ]
+[v isr@data_b data_b `uc  1 a 1 37 ]
+[v isr@data_a data_a `uc  1 a 1 36 ]
+"147
 } 0
-- 
cgit v1.2.1