From dd152f500f510bb59d261936466d5143f9592b05 Mon Sep 17 00:00:00 2001
From: Nao Pross <naopross@thearcway.org>
Date: Fri, 2 Mar 2018 10:01:32 +0100
Subject: Add automatic configuration and hardware bugfix (via sw)

---
 src/dist/default/production/src.production.sdb | 382 +++++++++----------------
 1 file changed, 142 insertions(+), 240 deletions(-)

(limited to 'src/dist/default/production/src.production.sdb')

diff --git a/src/dist/default/production/src.production.sdb b/src/dist/default/production/src.production.sdb
index c0c1673..46cff40 100644
--- a/src/dist/default/production/src.production.sdb
+++ b/src/dist/default/production/src.production.sdb
@@ -3,7 +3,17 @@
 [d edition pro ]
 [d chip 18F45K22 ]
 [d frameptr 4065 ]
-"232 Z:\SAMB_4\projects\xilofono\src\main.c
+"239 Z:\SAMB_4\projects\xilofono\src\main.c
+[e E52 . `uc
+NOTE_OFF 8
+NOTE_ON 9
+POLYPHONIC_KEYPRESS 10
+CONTROLLER 11
+PROGRAM_CHANGE 12
+CHANNEL_PRESSURE 13
+PITCH_BLEND 15
+]
+"244
 [e E43 . `uc
 C 0
 D 1
@@ -15,8 +25,8 @@ B 6
 ]
 "41 Z:\SAMB_4\projects\xilofono\src\midi.c
 [e E40 . `uc
-NOTE_ON 8
-NOTE_OFF 9
+NOTE_OFF 8
+NOTE_ON 9
 POLYPHONIC_KEYPRESS 10
 CONTROLLER 11
 PROGRAM_CHANGE 12
@@ -55,13 +65,13 @@ B 6
 [v ___flmul __flmul `(d  1 e 3 0 ]
 "15 C:\Program Files\Microchip\xc8\v1.44\sources\common\Umul32.c
 [v ___lmul __lmul `(ul  1 e 4 0 ]
-"113 Z:\SAMB_4\projects\xilofono\src\main.c
+"114 Z:\SAMB_4\projects\xilofono\src\main.c
 [v _isr isr `II(v  1 e 1 0 ]
-"150
+"156
 [v _init_hw init_hw `T(v  1 e 1 0 ]
-"215
+"221
 [v _main main `(v  1 e 1 0 ]
-"261
+"276
 [v _eusart_write_midi eusart_write_midi `(i  1 e 2 0 ]
 "40 Z:\SAMB_4\projects\xilofono\src\midi.c
 [v _midi_set_status midi_set_status `(i  1 e 2 0 ]
@@ -73,11 +83,11 @@ B 6
 [v _eusart1_init eusart1_init `(v  1 e 1 0 ]
 "25
 [v _eusart2_init eusart2_init `(v  1 e 1 0 ]
-"46
+"47
 [v _eusart1_putch eusart1_putch `(v  1 e 1 0 ]
-"52
+"53
 [v _eusart2_putch eusart2_putch `(v  1 e 1 0 ]
-"58
+"59
 [v _eusart1_getch eusart1_getch `(uc  1 e 1 0 ]
 "50 C:\Program Files\Microchip\xc8\v1.44\include\pic18f45k22.h
 [v _ANSELA ANSELA `VEuc  1 e 1 @3896 ]
@@ -87,7 +97,7 @@ B 6
 [v _ANSELC ANSELC `VEuc  1 e 1 @3898 ]
 "196
 [v _ANSELD ANSELD `VEuc  1 e 1 @3899 ]
-[s S784 . 1 `uc 1 ABDEN 1 0 :1:0 
+[s S481 . 1 `uc 1 ABDEN 1 0 :1:0 
 `uc 1 WUE 1 0 :1:1 
 `uc 1 . 1 0 :1:2 
 `uc 1 BRG16 1 0 :1:3 
@@ -97,10 +107,10 @@ B 6
 `uc 1 ABDOVF 1 0 :1:7 
 ]
 "4328
-[s S793 . 1 `uc 1 . 1 0 :4:0 
+[s S490 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 SCKP 1 0 :1:4 
 ]
-[s S1033 . 1 `uc 1 ABDEN2 1 0 :1:0 
+[s S730 . 1 `uc 1 ABDEN2 1 0 :1:0 
 `uc 1 WUE2 1 0 :1:1 
 `uc 1 . 1 0 :1:2 
 `uc 1 BRG162 1 0 :1:3 
@@ -109,14 +119,14 @@ B 6
 `uc 1 RCIDL2 1 0 :1:6 
 `uc 1 ABDOVF2 1 0 :1:7 
 ]
-[s S1042 . 1 `uc 1 . 1 0 :4:0 
+[s S739 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 TXCKP2 1 0 :1:4 
 `uc 1 RXDTP2 1 0 :1:5 
 `uc 1 RCMT2 1 0 :1:6 
 ]
-[u S1047 . 1 `S784 1 . 1 0 `S793 1 . 1 0 `S1033 1 . 1 0 `S1042 1 . 1 0 ]
-[v _BAUDCON2bits BAUDCON2bits `VES1047  1 e 1 @3952 ]
-[s S712 . 1 `uc 1 RX9D 1 0 :1:0 
+[u S744 . 1 `S481 1 . 1 0 `S490 1 . 1 0 `S730 1 . 1 0 `S739 1 . 1 0 ]
+[v _BAUDCON2bits BAUDCON2bits `VES744  1 e 1 @3952 ]
+[s S409 . 1 `uc 1 RX9D 1 0 :1:0 
 `uc 1 OERR 1 0 :1:1 
 `uc 1 FERR 1 0 :1:2 
 `uc 1 ADDEN 1 0 :1:3 
@@ -126,10 +136,10 @@ B 6
 `uc 1 SPEN 1 0 :1:7 
 ]
 "4593
-[s S721 . 1 `uc 1 . 1 0 :3:0 
+[s S418 . 1 `uc 1 . 1 0 :3:0 
 `uc 1 ADEN 1 0 :1:3 
 ]
-[s S968 . 1 `uc 1 RX9D2 1 0 :1:0 
+[s S665 . 1 `uc 1 RX9D2 1 0 :1:0 
 `uc 1 OERR2 1 0 :1:1 
 `uc 1 FERR2 1 0 :1:2 
 `uc 1 ADDEN2 1 0 :1:3 
@@ -138,16 +148,16 @@ B 6
 `uc 1 RX92 1 0 :1:6 
 `uc 1 SPEN2 1 0 :1:7 
 ]
-[s S977 . 1 `uc 1 RCD82 1 0 :1:0 
+[s S674 . 1 `uc 1 RCD82 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 RC8_92 1 0 :1:6 
 ]
-[s S981 . 1 `uc 1 . 1 0 :6:0 
+[s S678 . 1 `uc 1 . 1 0 :6:0 
 `uc 1 RC92 1 0 :1:6 
 ]
-[u S984 . 1 `S712 1 . 1 0 `S721 1 . 1 0 `S968 1 . 1 0 `S977 1 . 1 0 `S981 1 . 1 0 ]
-[v _RCSTA2bits RCSTA2bits `VES984  1 e 1 @3953 ]
-[s S663 . 1 `uc 1 TX9D 1 0 :1:0 
+[u S681 . 1 `S409 1 . 1 0 `S418 1 . 1 0 `S665 1 . 1 0 `S674 1 . 1 0 `S678 1 . 1 0 ]
+[v _RCSTA2bits RCSTA2bits `VES681  1 e 1 @3953 ]
+[s S360 . 1 `uc 1 TX9D 1 0 :1:0 
 `uc 1 TRMT 1 0 :1:1 
 `uc 1 BRGH 1 0 :1:2 
 `uc 1 SENDB 1 0 :1:3 
@@ -157,7 +167,7 @@ B 6
 `uc 1 CSRC 1 0 :1:7 
 ]
 "4873
-[s S916 . 1 `uc 1 TX9D2 1 0 :1:0 
+[s S613 . 1 `uc 1 TX9D2 1 0 :1:0 
 `uc 1 TRMT2 1 0 :1:1 
 `uc 1 BRGH2 1 0 :1:2 
 `uc 1 SENDB2 1 0 :1:3 
@@ -166,12 +176,12 @@ B 6
 `uc 1 TX92 1 0 :1:6 
 `uc 1 CSRC2 1 0 :1:7 
 ]
-[s S925 . 1 `uc 1 TXD82 1 0 :1:0 
+[s S622 . 1 `uc 1 TXD82 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 TX8_92 1 0 :1:6 
 ]
-[u S929 . 1 `S663 1 . 1 0 `S916 1 . 1 0 `S925 1 . 1 0 ]
-[v _TXSTA2bits TXSTA2bits `VES929  1 e 1 @3954 ]
+[u S626 . 1 `S360 1 . 1 0 `S613 1 . 1 0 `S622 1 . 1 0 ]
+[v _TXSTA2bits TXSTA2bits `VES626  1 e 1 @3954 ]
 "5093
 [v _TX2REG TX2REG `VEuc  1 e 1 @3955 ]
 "5164
@@ -180,133 +190,13 @@ B 6
 [v _SPBRGH2 SPBRGH2 `VEuc  1 e 1 @3958 ]
 "6278
 [v _PORTA PORTA `VEuc  1 e 1 @3968 ]
-[s S160 . 1 `uc 1 RA0 1 0 :1:0 
-`uc 1 RA1 1 0 :1:1 
-`uc 1 RA2 1 0 :1:2 
-`uc 1 RA3 1 0 :1:3 
-`uc 1 RA4 1 0 :1:4 
-`uc 1 RA5 1 0 :1:5 
-`uc 1 RA6 1 0 :1:6 
-`uc 1 RA7 1 0 :1:7 
-]
-"6363
-[s S169 . 1 `uc 1 AN0 1 0 :1:0 
-`uc 1 AN1 1 0 :1:1 
-`uc 1 AN2 1 0 :1:2 
-`uc 1 AN3 1 0 :1:3 
-`uc 1 . 1 0 :1:4 
-`uc 1 AN4 1 0 :1:5 
-]
-[s S176 . 1 `uc 1 C12IN0M 1 0 :1:0 
-`uc 1 C12IN1M 1 0 :1:1 
-`uc 1 C2INP 1 0 :1:2 
-`uc 1 C1INP 1 0 :1:3 
-`uc 1 C1OUT 1 0 :1:4 
-`uc 1 C2OUT 1 0 :1:5 
-]
-[s S183 . 1 `uc 1 C12IN0N 1 0 :1:0 
-`uc 1 C12IN1N 1 0 :1:1 
-`uc 1 VREFM 1 0 :1:2 
-`uc 1 VREFP 1 0 :1:3 
-`uc 1 T0CKI 1 0 :1:4 
-`uc 1 SS 1 0 :1:5 
-]
-[s S190 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 NOT_SS 1 0 :1:5 
-]
-[s S193 . 1 `uc 1 . 1 0 :2:0 
-`uc 1 VREFN 1 0 :1:2 
-`uc 1 . 1 0 :1:3 
-`uc 1 SRQ 1 0 :1:4 
-`uc 1 nSS 1 0 :1:5 
-]
-[s S199 . 1 `uc 1 . 1 0 :2:0 
-`uc 1 CVREF 1 0 :1:2 
-`uc 1 . 1 0 :2:3 
-`uc 1 LVDIN 1 0 :1:5 
-]
-[s S204 . 1 `uc 1 . 1 0 :2:0 
-`uc 1 DACOUT 1 0 :1:2 
-`uc 1 . 1 0 :2:3 
-`uc 1 HLVDIN 1 0 :1:5 
-]
-[s S209 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 SS1 1 0 :1:5 
-]
-[s S212 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 NOT_SS1 1 0 :1:5 
-]
-[s S215 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 nSS1 1 0 :1:5 
-]
-[s S218 . 1 `uc 1 . 1 0 :5:0 
-`uc 1 SRNQ 1 0 :1:5 
-]
-[s S221 . 1 `uc 1 ULPWUIN 1 0 :1:0 
-`uc 1 . 1 0 :6:1 
-`uc 1 RJPU 1 0 :1:7 
-]
-[u S225 . 1 `S160 1 . 1 0 `S169 1 . 1 0 `S176 1 . 1 0 `S183 1 . 1 0 `S190 1 . 1 0 `S193 1 . 1 0 `S199 1 . 1 0 `S204 1 . 1 0 `S209 1 . 1 0 `S212 1 . 1 0 `S215 1 . 1 0 `S218 1 . 1 0 `S221 1 . 1 0 ]
-[v _PORTAbits PORTAbits `VES225  1 e 1 @3968 ]
 "6563
 [v _PORTB PORTB `VEuc  1 e 1 @3969 ]
-[s S21 . 1 `uc 1 RD0 1 0 :1:0 
-`uc 1 RD1 1 0 :1:1 
-`uc 1 RD2 1 0 :1:2 
-`uc 1 RD3 1 0 :1:3 
-`uc 1 RD4 1 0 :1:4 
-`uc 1 RD5 1 0 :1:5 
-`uc 1 RD6 1 0 :1:6 
-`uc 1 RD7 1 0 :1:7 
-]
-"7203
-[s S30 . 1 `uc 1 . 1 0 :2:0 
-`uc 1 P2B 1 0 :1:2 
-`uc 1 P2C 1 0 :1:3 
-`uc 1 P2D 1 0 :1:4 
-`uc 1 P1B 1 0 :1:5 
-`uc 1 P1C 1 0 :1:6 
-`uc 1 P1D 1 0 :1:7 
-]
-[s S38 . 1 `uc 1 . 1 0 :1:0 
-`uc 1 CCP4 1 0 :1:1 
-`uc 1 . 1 0 :4:2 
-`uc 1 TX2 1 0 :1:6 
-`uc 1 RX2 1 0 :1:7 
-]
-[s S44 . 1 `uc 1 . 1 0 :3:0 
-`uc 1 NOT_SS2 1 0 :1:3 
-]
-[s S47 . 1 `uc 1 SCK2 1 0 :1:0 
-`uc 1 SDI2 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 nSS2 1 0 :1:3 
-`uc 1 SDO2 1 0 :1:4 
-`uc 1 . 1 0 :1:5 
-`uc 1 CK2 1 0 :1:6 
-`uc 1 DT2 1 0 :1:7 
-]
-[s S56 . 1 `uc 1 SCL2 1 0 :1:0 
-`uc 1 SDA2 1 0 :1:1 
-`uc 1 . 1 0 :1:2 
-`uc 1 SS2 1 0 :1:3 
-]
-[s S61 . 1 `uc 1 AN20 1 0 :1:0 
-`uc 1 AN21 1 0 :1:1 
-`uc 1 AN22 1 0 :1:2 
-`uc 1 AN23 1 0 :1:3 
-`uc 1 AN24 1 0 :1:4 
-`uc 1 AN25 1 0 :1:5 
-`uc 1 AN26 1 0 :1:6 
-`uc 1 AN27 1 0 :1:7 
-]
-[u S70 . 1 `S21 1 . 1 0 `S30 1 . 1 0 `S38 1 . 1 0 `S44 1 . 1 0 `S47 1 . 1 0 `S56 1 . 1 0 `S61 1 . 1 0 ]
-[v _PORTDbits PORTDbits `VES70  1 e 1 @3971 ]
 "8058
 [v _TRISA TRISA `VEuc  1 e 1 @3986 ]
 "8280
 [v _TRISB TRISB `VEuc  1 e 1 @3987 ]
-[s S867 . 1 `uc 1 TRISC0 1 0 :1:0 
+[s S564 . 1 `uc 1 TRISC0 1 0 :1:0 
 `uc 1 TRISC1 1 0 :1:1 
 `uc 1 TRISC2 1 0 :1:2 
 `uc 1 TRISC3 1 0 :1:3 
@@ -316,7 +206,7 @@ B 6
 `uc 1 TRISC7 1 0 :1:7 
 ]
 "8534
-[s S876 . 1 `uc 1 RC0 1 0 :1:0 
+[s S573 . 1 `uc 1 RC0 1 0 :1:0 
 `uc 1 RC1 1 0 :1:1 
 `uc 1 RC2 1 0 :1:2 
 `uc 1 RC3 1 0 :1:3 
@@ -325,9 +215,9 @@ B 6
 `uc 1 RC6 1 0 :1:6 
 `uc 1 RC7 1 0 :1:7 
 ]
-[u S885 . 1 `S867 1 . 1 0 `S876 1 . 1 0 ]
-[v _TRISCbits TRISCbits `VES885  1 e 1 @3988 ]
-[s S418 . 1 `uc 1 TRISD0 1 0 :1:0 
+[u S582 . 1 `S564 1 . 1 0 `S573 1 . 1 0 ]
+[v _TRISCbits TRISCbits `VES582  1 e 1 @3988 ]
+[s S776 . 1 `uc 1 TRISD0 1 0 :1:0 
 `uc 1 TRISD1 1 0 :1:1 
 `uc 1 TRISD2 1 0 :1:2 
 `uc 1 TRISD3 1 0 :1:3 
@@ -337,23 +227,32 @@ B 6
 `uc 1 TRISD7 1 0 :1:7 
 ]
 "8756
-[u S436 . 1 `S418 1 . 1 0 `S21 1 . 1 0 ]
-[v _TRISDbits TRISDbits `VES436  1 e 1 @3989 ]
-[s S354 . 1 `uc 1 TUN 1 0 :6:0 
+[s S785 . 1 `uc 1 RD0 1 0 :1:0 
+`uc 1 RD1 1 0 :1:1 
+`uc 1 RD2 1 0 :1:2 
+`uc 1 RD3 1 0 :1:3 
+`uc 1 RD4 1 0 :1:4 
+`uc 1 RD5 1 0 :1:5 
+`uc 1 RD6 1 0 :1:6 
+`uc 1 RD7 1 0 :1:7 
+]
+[u S794 . 1 `S776 1 . 1 0 `S785 1 . 1 0 ]
+[v _TRISDbits TRISDbits `VES794  1 e 1 @3989 ]
+[s S102 . 1 `uc 1 TUN 1 0 :6:0 
 `uc 1 PLLEN 1 0 :1:6 
 `uc 1 INTSRC 1 0 :1:7 
 ]
 "9082
-[s S358 . 1 `uc 1 TUN0 1 0 :1:0 
+[s S106 . 1 `uc 1 TUN0 1 0 :1:0 
 `uc 1 TUN1 1 0 :1:1 
 `uc 1 TUN2 1 0 :1:2 
 `uc 1 TUN3 1 0 :1:3 
 `uc 1 TUN4 1 0 :1:4 
 `uc 1 TUN5 1 0 :1:5 
 ]
-[u S365 . 1 `S354 1 . 1 0 `S358 1 . 1 0 ]
-[v _OSCTUNEbits OSCTUNEbits `VES365  1 e 1 @3995 ]
-[s S487 . 1 `uc 1 TMR1IE 1 0 :1:0 
+[u S113 . 1 `S102 1 . 1 0 `S106 1 . 1 0 ]
+[v _OSCTUNEbits OSCTUNEbits `VES113  1 e 1 @3995 ]
+[s S195 . 1 `uc 1 TMR1IE 1 0 :1:0 
 `uc 1 TMR2IE 1 0 :1:1 
 `uc 1 CCP1IE 1 0 :1:2 
 `uc 1 SSP1IE 1 0 :1:3 
@@ -362,14 +261,14 @@ B 6
 `uc 1 ADIE 1 0 :1:6 
 ]
 "9434
-[s S495 . 1 `uc 1 . 1 0 :3:0 
+[s S203 . 1 `uc 1 . 1 0 :3:0 
 `uc 1 SSPIE 1 0 :1:3 
 `uc 1 TXIE 1 0 :1:4 
 `uc 1 RCIE 1 0 :1:5 
 ]
-[u S500 . 1 `S487 1 . 1 0 `S495 1 . 1 0 ]
-[v _PIE1bits PIE1bits `VES500  1 e 1 @3997 ]
-[s S128 . 1 `uc 1 TMR1IF 1 0 :1:0 
+[u S208 . 1 `S195 1 . 1 0 `S203 1 . 1 0 ]
+[v _PIE1bits PIE1bits `VES208  1 e 1 @3997 ]
+[s S21 . 1 `uc 1 TMR1IF 1 0 :1:0 
 `uc 1 TMR2IF 1 0 :1:1 
 `uc 1 CCP1IF 1 0 :1:2 
 `uc 1 SSP1IF 1 0 :1:3 
@@ -378,15 +277,15 @@ B 6
 `uc 1 ADIF 1 0 :1:6 
 ]
 "9511
-[s S136 . 1 `uc 1 . 1 0 :3:0 
+[s S29 . 1 `uc 1 . 1 0 :3:0 
 `uc 1 SSPIF 1 0 :1:3 
 `uc 1 TXIF 1 0 :1:4 
 `uc 1 RCIF 1 0 :1:5 
 ]
-[u S141 . 1 `S128 1 . 1 0 `S136 1 . 1 0 ]
-[v _PIR1bits PIR1bits `VES141  1 e 1 @3998 ]
+[u S34 . 1 `S21 1 . 1 0 `S29 1 . 1 0 ]
+[v _PIR1bits PIR1bits `VES34  1 e 1 @3998 ]
 "10396
-[s S724 . 1 `uc 1 RX9D1 1 0 :1:0 
+[s S421 . 1 `uc 1 RX9D1 1 0 :1:0 
 `uc 1 OERR1 1 0 :1:1 
 `uc 1 FERR1 1 0 :1:2 
 `uc 1 ADDEN1 1 0 :1:3 
@@ -395,20 +294,20 @@ B 6
 `uc 1 RX91 1 0 :1:6 
 `uc 1 SPEN1 1 0 :1:7 
 ]
-[s S733 . 1 `uc 1 RCD8 1 0 :1:0 
+[s S430 . 1 `uc 1 RCD8 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 RC8_9 1 0 :1:6 
 ]
-[s S737 . 1 `uc 1 . 1 0 :6:0 
+[s S434 . 1 `uc 1 . 1 0 :6:0 
 `uc 1 RC9 1 0 :1:6 
 ]
-[s S740 . 1 `uc 1 . 1 0 :5:0 
+[s S437 . 1 `uc 1 . 1 0 :5:0 
 `uc 1 SRENA 1 0 :1:5 
 ]
-[u S743 . 1 `S712 1 . 1 0 `S721 1 . 1 0 `S724 1 . 1 0 `S733 1 . 1 0 `S737 1 . 1 0 `S740 1 . 1 0 ]
-[v _RCSTA1bits RCSTA1bits `VES743  1 e 1 @4011 ]
+[u S440 . 1 `S409 1 . 1 0 `S418 1 . 1 0 `S421 1 . 1 0 `S430 1 . 1 0 `S434 1 . 1 0 `S437 1 . 1 0 ]
+[v _RCSTA1bits RCSTA1bits `VES440  1 e 1 @4011 ]
 "10840
-[s S672 . 1 `uc 1 TX9D1 1 0 :1:0 
+[s S369 . 1 `uc 1 TX9D1 1 0 :1:0 
 `uc 1 TRMT1 1 0 :1:1 
 `uc 1 BRGH1 1 0 :1:2 
 `uc 1 SENDB1 1 0 :1:3 
@@ -417,12 +316,12 @@ B 6
 `uc 1 TX91 1 0 :1:6 
 `uc 1 CSRC1 1 0 :1:7 
 ]
-[s S681 . 1 `uc 1 TXD8 1 0 :1:0 
+[s S378 . 1 `uc 1 TXD8 1 0 :1:0 
 `uc 1 . 1 0 :5:1 
 `uc 1 TX8_9 1 0 :1:6 
 ]
-[u S685 . 1 `S663 1 . 1 0 `S672 1 . 1 0 `S681 1 . 1 0 ]
-[v _TXSTA1bits TXSTA1bits `VES685  1 e 1 @4012 ]
+[u S382 . 1 `S360 1 . 1 0 `S369 1 . 1 0 `S378 1 . 1 0 ]
+[v _TXSTA1bits TXSTA1bits `VES382  1 e 1 @4012 ]
 "11183
 [v _TX1REG TX1REG `VEuc  1 e 1 @4013 ]
 "11261
@@ -432,7 +331,7 @@ B 6
 "11408
 [v _SPBRGH1 SPBRGH1 `VEuc  1 e 1 @4016 ]
 "12436
-[s S796 . 1 `uc 1 ABDEN1 1 0 :1:0 
+[s S493 . 1 `uc 1 ABDEN1 1 0 :1:0 
 `uc 1 WUE1 1 0 :1:1 
 `uc 1 . 1 0 :1:2 
 `uc 1 BRG161 1 0 :1:3 
@@ -441,30 +340,30 @@ B 6
 `uc 1 RCIDL1 1 0 :1:6 
 `uc 1 ABDOVF1 1 0 :1:7 
 ]
-[s S805 . 1 `uc 1 . 1 0 :4:0 
+[s S502 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 TXCKP 1 0 :1:4 
 `uc 1 RXDTP 1 0 :1:5 
 `uc 1 RCMT 1 0 :1:6 
 ]
-[s S810 . 1 `uc 1 . 1 0 :4:0 
+[s S507 . 1 `uc 1 . 1 0 :4:0 
 `uc 1 TXCKP1 1 0 :1:4 
 `uc 1 RXDTP1 1 0 :1:5 
 `uc 1 RCMT1 1 0 :1:6 
 ]
-[s S815 . 1 `uc 1 . 1 0 :5:0 
+[s S512 . 1 `uc 1 . 1 0 :5:0 
 `uc 1 RXCKP 1 0 :1:5 
 ]
-[s S818 . 1 `uc 1 . 1 0 :1:0 
+[s S515 . 1 `uc 1 . 1 0 :1:0 
 `uc 1 W4E 1 0 :1:1 
 ]
-[u S821 . 1 `S784 1 . 1 0 `S793 1 . 1 0 `S796 1 . 1 0 `S805 1 . 1 0 `S810 1 . 1 0 `S815 1 . 1 0 `S818 1 . 1 0 ]
-[v _BAUDCON1bits BAUDCON1bits `VES821  1 e 1 @4024 ]
-[s S459 . 1 `uc 1 T2CKPS 1 0 :2:0 
+[u S518 . 1 `S481 1 . 1 0 `S490 1 . 1 0 `S493 1 . 1 0 `S502 1 . 1 0 `S507 1 . 1 0 `S512 1 . 1 0 `S515 1 . 1 0 ]
+[v _BAUDCON1bits BAUDCON1bits `VES518  1 e 1 @4024 ]
+[s S167 . 1 `uc 1 T2CKPS 1 0 :2:0 
 `uc 1 TMR2ON 1 0 :1:2 
 `uc 1 T2OUTPS 1 0 :4:3 
 ]
 "13217
-[s S463 . 1 `uc 1 T2CKPS0 1 0 :1:0 
+[s S171 . 1 `uc 1 T2CKPS0 1 0 :1:0 
 `uc 1 T2CKPS1 1 0 :1:1 
 `uc 1 . 1 0 :1:2 
 `uc 1 T2OUTPS0 1 0 :1:3 
@@ -472,18 +371,18 @@ B 6
 `uc 1 T2OUTPS2 1 0 :1:5 
 `uc 1 T2OUTPS3 1 0 :1:6 
 ]
-[u S471 . 1 `S459 1 . 1 0 `S463 1 . 1 0 ]
-[v _T2CONbits T2CONbits `VES471  1 e 1 @4026 ]
+[u S179 . 1 `S167 1 . 1 0 `S171 1 . 1 0 ]
+[v _T2CONbits T2CONbits `VES179  1 e 1 @4026 ]
 "13267
 [v _PR2 PR2 `VEuc  1 e 1 @4027 ]
-[s S380 . 1 `uc 1 SCS 1 0 :2:0 
+[s S128 . 1 `uc 1 SCS 1 0 :2:0 
 `uc 1 HFIOFS 1 0 :1:2 
 `uc 1 OSTS 1 0 :1:3 
 `uc 1 IRCF 1 0 :3:4 
 `uc 1 IDLEN 1 0 :1:7 
 ]
 "16033
-[s S386 . 1 `uc 1 SCS0 1 0 :1:0 
+[s S134 . 1 `uc 1 SCS0 1 0 :1:0 
 `uc 1 SCS1 1 0 :1:1 
 `uc 1 IOFS 1 0 :1:2 
 `uc 1 . 1 0 :1:3 
@@ -491,9 +390,9 @@ B 6
 `uc 1 IRCF1 1 0 :1:5 
 `uc 1 IRCF2 1 0 :1:6 
 ]
-[u S394 . 1 `S380 1 . 1 0 `S386 1 . 1 0 ]
-[v _OSCCONbits OSCCONbits `VES394  1 e 1 @4051 ]
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cgit v1.2.1