From 65a4baa17b439e1bdf42b6c0150a52e032562bb5 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 18 Jan 2018 10:28:49 +0100 Subject: Move to version control --- src/main.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 src/main.c (limited to 'src/main.c') diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..da15d3a --- /dev/null +++ b/src/main.c @@ -0,0 +1,91 @@ +/* + * File: main.c + * Author: _prossn + * Date: 08.01.2018 + * Target: PIC18F44K22 + * Version 1.0 + * + * Description: + * + * Main program for the Xylophone project. + */ + +// PIC18F44K22 Configuration Bit Settings +// 'C' source line config statements + +// CONFIG1H +#pragma config FOSC = ECHPIO6 // Oscillator Selection bits (EC oscillator (high power, >16 MHz)) +#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly) +#pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled) +#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) +#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) + +// CONFIG2L +#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled) +#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) +#pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal) + +// CONFIG2H +#pragma config WDTEN = ON // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect) +#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) + +// CONFIG3H +#pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) +#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset) +#pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5) +#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status) +#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0) +#pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2) +#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled) + +// CONFIG4L +#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) +#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1) +#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) + +// CONFIG5L +#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) +#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) + +// CONFIG5H +#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) +#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) + +// CONFIG6L +#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) +#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) + +// CONFIG6H +#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) +#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) +#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) + +// CONFIG7L +#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) +#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) + +// CONFIG7H +#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) + +// #pragma config statements should precede project file includes. +// Use project enums instead of #define for ON and OFF. + +#include "rs232.h" + +#include +#include +#include +#include + + +/* main program */ +void main(void) { + + eusart_init(); + + /* main loop */ + while (1) { + + } +} + -- cgit v1.2.1