Disassembly Listing for Xilofono Generated From: Z:/SAMB_4/projects/xilofono/src/dist/default/production/src.production.elf 27-feb-2018 09:19:21 --- Z:/SAMB_4/projects/xilofono/src/rs232.c ----------------------------------------------------------- 1: #include "rs232.h" 2: #include 3: 4: void eusart1_init(void) 5: { 6: // set Async and 8 bits frame 7: TXSTA1bits.SYNC = 0; 0598 98AC BCF TXSTA1, 4, ACCESS 8: TXSTA1bits.TX9 = 0; 059A 9CAC BCF TXSTA1, 6, ACCESS 9: 10: // baud prescaler 11: RCSTA1bits.SPEN = 1; 059C 8EAB BSF RCSTA1, 7, ACCESS 12: SPBRG1 = 31; 059E 0E1F MOVLW 0x1F 05A0 6EAF MOVWF SPBRG1, ACCESS 13: SPBRGH1 = 0; 05A2 0E00 MOVLW 0x0 05A4 6EB0 MOVWF SPBRGH1, ACCESS 14: TXSTA1bits.BRGH = 0; 05A6 94AC BCF TXSTA1, 2, ACCESS 15: BAUDCON1bits.BRG16 = 0; 05A8 96B8 BCF BAUDCON1, 3, ACCESS 16: 17: // set up TX / RX pins 18: TRISCbits.TRISC7 = 1; 05AA 8E94 BSF TRISC, 7, ACCESS 19: TRISCbits.TRISC6 = 1; 05AC 8C94 BSF TRISC, 6, ACCESS 20: RCSTA1bits.CREN = 1; // enable continuous reception 05AE 88AB BSF RCSTA1, 4, ACCESS 21: TXSTA1bits.TXEN = 1; 05B0 8AAC BSF TXSTA1, 5, ACCESS 22: } 05B2 0012 RETURN 0 23: 24: void eusart2_init(void) 25: { 26: // TODO 27: } 28: 29: void putch(char c) 05B4 0100 MOVLB 0x0 05B6 6F60 MOVWF __pcstackBANK0, BANKED 30: { 31: while (!TX1IF); 05B8 A89E BTFSS PIR1, 4, ACCESS 05BA D7FE BRA 0x5B8 32: TX1REG = c; 05BC C060 MOVFF __pcstackBANK0, TXREG1 05BE FFAD NOP 33: } 0008 8245 BSF btemp, 1, ACCESS 000A CFFA MOVFF PCLATH, 0x2B 000C F02B NOP 000E CFFB MOVFF PCLATU, 0x2C 0010 F02C NOP 0012 CFE9 MOVFF FSR0, 0x2D 0014 F02D NOP 0016 CFEA MOVFF FSR0H, 0x2E 0018 F02E NOP 001A CFE1 MOVFF FSR1, 0x2F 001C F02F NOP 001E CFE2 MOVFF FSR1H, 0x30 0020 F030 NOP 0022 CFD9 MOVFF FSR2, 0x31 0024 F031 NOP 0026 CFDA MOVFF FSR2H, 0x32 0028 F032 NOP 002A CFF3 MOVFF PROD, 0x33 002C F033 NOP 002E CFF4 MOVFF PRODH, 0x34 0030 F034 NOP 0032 CFF6 MOVFF TBLPTR, 0x35 0034 F035 NOP 0036 CFF7 MOVFF TBLPTRH, 0x36 0038 F036 NOP 003A CFF8 MOVFF TBLPTRU, 0x37 003C F037 NOP 003E CFF5 MOVFF TABLAT, 0x38 0040 F038 NOP 0042 C045 MOVFF btemp, 0x39 0044 F039 NOP 0046 C046 MOVFF 0x46, 0x3A 0048 F03A NOP 004A C047 MOVFF 0x47, 0x3B 004C F03B NOP 004E C048 MOVFF 0x48, 0x3C 0050 F03C NOP 05C0 0012 RETURN 0 34: 35: char getch(void) 36: { 37: while (!RC1IF); 38: return RC1REG; 39: } 40: 41: char getche(void) 42: { 43: char c = getch(); 44: putch(c); // echo 45: 46: return c; 47: } --- Z:/SAMB_4/projects/xilofono/src/midi.c ------------------------------------------------------------ 1: #include "midi.h" 2: 3: #include 4: #include 5: #include 6: #include 7: 8: 9: #ifdef MIDI_DYNAMIC_MEMORY_ALLOC 10: midi_message_t *midi_alloc_message(size_t data_size) 11: { 12: return (midi_message_t *) malloc(sizeof(midi_message_t) + data_size); 13: } 14: 15: void midi_free_message(midi_message_t *pkt) 16: { 17: if (pkt == NULL) { 18: return; 19: } 20: 21: free(pkt); 22: pkt = NULL; 23: } 24: 25: size_t midi_message_size(const midi_message_t *pkt) 26: { 27: if (pkt == NULL) { 28: return 0; 29: } 30: 31: switch (pkt->status) { 32: case NOTE_ON: return sizeof(midi_message_t) + 2; 33: case NOTE_OFF: return sizeof(midi_message_t) + 1; 34: default: return sizeof(midi_message_t); 35: } 36: } 37: #endif 38: 39: 40: int midi_set_status(midi_message_t *pkt, midi_status_t status) 41: { 42: if (pkt == NULL) { 0572 0100 MOVLB 0x0 0574 5160 MOVF __pcstackBANK0, W, BANKED 0576 1161 IORWF pkt, W, BANKED 0578 B4D8 BTFSC STATUS, 2, ACCESS 057A 0012 RETURN 0 43: return -1; 44: } 45: 46: pkt->status = status & 0x0F; 057C C062 MOVFF c, 0x63 057E F063 NOP 0580 0E0F MOVLW 0xF 0582 1763 ANDWF 0x63, F, BANKED 0584 C060 MOVFF __pcstackBANK0, FSR2 0586 FFD9 NOP 0588 C061 MOVFF pkt, FSR2H 058A FFDA NOP 058C 50DF MOVF INDF2, W, ACCESS 058E 1963 XORWF 0x63, W, BANKED 0590 0BF0 ANDLW 0xF0 0592 1963 XORWF 0x63, W, BANKED 0594 6EDF MOVWF INDF2, ACCESS 0596 0012 RETURN 0 47: 48: return 0; 49: } 50: 51: int midi_set_channel(midi_message_t *pkt, unsigned channel) 52: { 53: if (pkt == NULL) { 054A 0100 MOVLB 0x0 054C 5160 MOVF __pcstackBANK0, W, BANKED 054E 1161 IORWF pkt, W, BANKED 0550 B4D8 BTFSC STATUS, 2, ACCESS 0552 0012 RETURN 0 54: return -1; 55: } 56: 57: pkt->channel = channel & 0x0F; 0554 C062 MOVFF c, n 0556 F064 NOP 0558 0E0F MOVLW 0xF 055A 1764 ANDWF n, F, BANKED 055C C060 MOVFF __pcstackBANK0, FSR2 055E FFD9 NOP 0560 C061 MOVFF pkt, FSR2H 0562 FFDA NOP 0564 3B64 SWAPF n, F, BANKED 0566 50DF MOVF INDF2, W, ACCESS 0568 1964 XORWF n, W, BANKED 056A 0B0F ANDLW 0xF 056C 1964 XORWF n, W, BANKED 056E 6EDF MOVWF INDF2, ACCESS 0570 0012 RETURN 0 58: 59: return 0; 60: } 61: 62: int midi_note_on(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity) 63: { 64: if (pkt == NULL) { 0424 0100 MOVLB 0x0 0426 5165 MOVF pkt, W, BANKED 0428 1166 IORWF p, W, BANKED 042A B4D8 BTFSC STATUS, 2, ACCESS 042C 0012 RETURN 0 65: return -1; 66: } 67: 68: #ifdef MIDI_DYNAMIC_MEMORY_ALLOC 69: if (pkt->data == NULL) { 70: return -2; 71: } 72: #endif 73: 74: midi_set_status(pkt, NOTE_ON); 042E C065 MOVFF pkt, __pcstackBANK0 0430 F060 NOP 0432 C066 MOVFF p, pkt 0434 F061 NOP 0436 0E08 MOVLW 0x8 0438 6F62 MOVWF c, BANKED 043A ECB9 CALL 0x572, 0 043C F002 NOP 75: midi_set_channel(pkt, channel); 043E C065 MOVFF pkt, __pcstackBANK0 0440 F060 NOP 0442 C066 MOVFF p, pkt 0444 F061 NOP 0446 C067 MOVFF channel, c 0448 F062 NOP 044A C068 MOVFF 0x68, 0x63 044C F063 NOP 044E ECA5 CALL 0x54A, 0 0450 F002 NOP 76: 77: pkt->data[0] = note; 0452 0100 MOVLB 0x0 0454 EE20 LFSR 2, 0x3 0456 F003 NOP 0458 5165 MOVF pkt, W, BANKED 045A 26D9 ADDWF FSR2, F, ACCESS 045C 5166 MOVF p, W, BANKED 045E 22DA ADDWFC FSR2H, F, ACCESS 0460 C069 MOVFF note, INDF2 0462 FFDF NOP 78: pkt->data[1] = velocity; 0464 EE20 LFSR 2, 0x4 0466 F004 NOP 0468 5165 MOVF pkt, W, BANKED 046A 26D9 ADDWF FSR2, F, ACCESS 046C 5166 MOVF p, W, BANKED 046E 22DA ADDWFC FSR2H, F, ACCESS 0470 C06A MOVFF velocity, INDF2 0472 FFDF NOP 79: 80: #ifndef MIDI_DYNAMIC_MEMORY_ALLOC 81: pkt->data_size = 2; 0474 EE20 LFSR 2, 0x1 0476 F001 NOP 0478 5165 MOVF pkt, W, BANKED 047A 26D9 ADDWF FSR2, F, ACCESS 047C 5166 MOVF p, W, BANKED 047E 22DA ADDWFC FSR2H, F, ACCESS 0480 0E02 MOVLW 0x2 0482 6EDE MOVWF POSTINC2, ACCESS 0484 0E00 MOVLW 0x0 0486 6EDD MOVWF POSTDEC2, ACCESS 0488 0012 RETURN 0 82: #endif 83: 84: return 0; 85: } 86: 87: int midi_note_off(midi_message_t *pkt, unsigned channel, midi_note_t note, uint8_t velocity) 88: { 89: if (pkt == NULL) { 90: return -1; 91: } 92: 93: #ifdef MIDI_DYNAMIC_MEMORY_ALLOC 94: if (pkt->data == NULL) { 95: return -2; 96: } 97: #endif 98: 99: midi_set_status(pkt, NOTE_OFF); 100: midi_set_channel(pkt, channel); 101: 102: pkt->data[0] = note; 103: pkt->data[1] = velocity; 104: 105: #ifndef MIDI_DYNAMIC_MEMORY_ALLOC 106: pkt->data_size = 2; 107: #endif 108: 109: return 0; 110: } --- Z:/SAMB_4/projects/xilofono/src/main.c ------------------------------------------------------------ 1: /* 2: * File: main.c 3: * Author: Naoki Pross 4E 4: * Date: 08.01.2018 5: * Target: PIC18F44K22 6: * Version 1.0 7: * 8: * Description: 9: * 10: * Main program for the Xylophone project. 11: */ 12: 13: // PIC18F44K22 Configuration Bit Settings 14: // 'C' source line config statements 15: 16: // CONFIG1H 17: #pragma config FOSC = INTIO7 // Oscillator Selection bits (Internal oscillator block) 18: #pragma config PLLCFG = ON // 4X PLL Enable (Oscillator multiplied by 4) 19: #pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled) 20: #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) 21: #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) 22: 23: // CONFIG2L 24: #pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled) 25: #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) 26: #pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal) 27: 28: // CONFIG2H 29: #pragma config WDTEN = ON // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect) 30: #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) 31: 32: // CONFIG3H 33: #pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) 34: #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset) 35: #pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5) 36: #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status) 37: #pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0) 38: #pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2) 39: #pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled) 40: 41: // CONFIG4L 42: #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) 43: #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1) 44: #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) 45: 46: // CONFIG5L 47: #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) 48: #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) 49: #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) 50: #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) 51: 52: // CONFIG5H 53: #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) 54: #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) 55: 56: // CONFIG6L 57: #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) 58: #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) 59: #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) 60: #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) 61: 62: // CONFIG6H 63: #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) 64: #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) 65: #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) 66: 67: // CONFIG7L 68: #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) 69: #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) 70: #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) 71: #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) 72: 73: // CONFIG7H 74: #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) 75: 76: // #pragma config statements should precede project file includes. 77: // Use project enums instead of #define for ON and OFF. 78: 79: #define _XTAL_FREQ 64000000 80: 81: #include "rs232.h" 82: #include "midi.h" 83: 84: #include 85: #include 86: #include 87: #include 88: #include 89: 90: #define NOTES 16 91: #define NOTE_MASK 0xFF00 92: 93: #define MIDI_CHANNEL 0x0 94: #define MIDI_SCALE_START 0x3C 95: 96: /* global variables */ 97: volatile uint16_t keys_data[NOTES]; 98: volatile uint16_t keypresses = 0; // flags to notify the main program 99: 100: /* function prototypes */ 101: int eusart_write_midi(const midi_message_t *pkt); 102: 103: /* interrupt service routine */ 104: interrupt void isr(void) 0008 8245 BSF btemp, 1, ACCESS 105: { 106: unsigned char i, data_a, data_b; 107: 108: PORTDbits.RD3 = 0; 0052 9683 BCF PORTD, 3, ACCESS 109: 110: if (PIR1bits.TMR2IF) { 0054 A29E BTFSS PIR1, 1, ACCESS 0056 D11F BRA 0x296 111: data_a = PORTA; 0058 CF80 MOVFF PORTA, data_a 005A F03D NOP 112: data_b = PORTB; 005C CF81 MOVFF PORTB, data_b 005E F03E NOP 113: i = 7; 0060 0E07 MOVLW 0x7 0062 6E42 MOVWF i, ACCESS 114: do { 115: // read the data and append it at the end of keys_data[i] 116: keys_data[i] = (keys_data[i] << 1) | ((data_a >> i) & 0x01); 0064 5042 MOVF i, W, ACCESS 0066 0D02 MULLW 0x2 0068 0E03 MOVLW 0x3 006A 24F3 ADDWF PROD, W, ACCESS 006C 6ED9 MOVWF FSR2, ACCESS 006E 0E00 MOVLW 0x0 0070 20F4 ADDWFC PRODH, W, ACCESS 0072 6EDA MOVWF FSR2H, ACCESS 0074 CFDE MOVFF POSTINC2, __pcstackCOMRAM 0076 F023 NOP 0078 CFDD MOVFF POSTDEC2, 0x24 007A F024 NOP 007C 90D8 BCF STATUS, 0, ACCESS 007E 3623 RLCF __pcstackCOMRAM, F, ACCESS 0080 3624 RLCF 0x24, F, ACCESS 0082 C042 MOVFF i, 0x25 0084 F025 NOP 0086 C03D MOVFF data_a, 0x26 0088 F026 NOP 008A 2A25 INCF 0x25, F, ACCESS 008C D002 BRA 0x92 008E 90D8 BCF STATUS, 0, ACCESS 0090 3226 RRCF 0x26, F, ACCESS 0092 2E25 DECFSZ 0x25, F, ACCESS 0094 D7FC BRA 0x8E 0096 0E01 MOVLW 0x1 0098 1626 ANDWF 0x26, F, ACCESS 009A 5026 MOVF 0x26, W, ACCESS 009C 1223 IORWF __pcstackCOMRAM, F, ACCESS 009E 0E00 MOVLW 0x0 00A0 1224 IORWF 0x24, F, ACCESS 00A2 5042 MOVF i, W, ACCESS 00A4 0D02 MULLW 0x2 00A6 0E03 MOVLW 0x3 00A8 24F3 ADDWF PROD, W, ACCESS 00AA 6ED9 MOVWF FSR2, ACCESS 00AC 0E00 MOVLW 0x0 00AE 20F4 ADDWFC PRODH, W, ACCESS 00B0 6EDA MOVWF FSR2H, ACCESS 00B2 C023 MOVFF __pcstackCOMRAM, POSTINC2 00B4 FFDE NOP 00B6 C024 MOVFF 0x24, POSTDEC2 00B8 FFDD NOP 117: keys_data[i + 8] = (keys_data[i + 8] << 1) | ((data_b >> i) & 0x01); 00BA 5042 MOVF i, W, ACCESS 00BC 6E23 MOVWF __pcstackCOMRAM, ACCESS 00BE 6A24 CLRF 0x24, ACCESS 00C0 90D8 BCF STATUS, 0, ACCESS 00C2 3623 RLCF __pcstackCOMRAM, F, ACCESS 00C4 3624 RLCF 0x24, F, ACCESS 00C6 0E10 MOVLW 0x10 00C8 2623 ADDWF __pcstackCOMRAM, F, ACCESS 00CA 0E00 MOVLW 0x0 00CC 2224 ADDWFC 0x24, F, ACCESS 00CE 0E03 MOVLW 0x3 00D0 2423 ADDWF __pcstackCOMRAM, W, ACCESS 00D2 6ED9 MOVWF FSR2, ACCESS 00D4 0E00 MOVLW 0x0 00D6 2024 ADDWFC 0x24, W, ACCESS 00D8 6EDA MOVWF FSR2H, ACCESS 00DA CFDE MOVFF POSTINC2, 0x25 00DC F025 NOP 00DE CFDD MOVFF POSTDEC2, 0x26 00E0 F026 NOP 00E2 90D8 BCF STATUS, 0, ACCESS 00E4 3625 RLCF 0x25, F, ACCESS 00E6 3626 RLCF 0x26, F, ACCESS 00E8 C042 MOVFF i, 0x27 00EA F027 NOP 00EC C03E MOVFF data_b, 0x28 00EE F028 NOP 00F0 2A27 INCF 0x27, F, ACCESS 00F2 D002 BRA 0xF8 00F4 90D8 BCF STATUS, 0, ACCESS 00F6 3228 RRCF 0x28, F, ACCESS 00F8 2E27 DECFSZ 0x27, F, ACCESS 00FA D7FC BRA 0xF4 00FC 0E01 MOVLW 0x1 00FE 1628 ANDWF 0x28, F, ACCESS 0100 5028 MOVF 0x28, W, ACCESS 0102 1225 IORWF 0x25, F, ACCESS 0104 0E00 MOVLW 0x0 0106 1226 IORWF 0x26, F, ACCESS 0108 5042 MOVF i, W, ACCESS 010A 6E29 MOVWF 0x29, ACCESS 010C 6A2A CLRF 0x2A, ACCESS 010E 90D8 BCF STATUS, 0, ACCESS 0110 3629 RLCF 0x29, F, ACCESS 0112 362A RLCF 0x2A, F, ACCESS 0114 0E10 MOVLW 0x10 0116 2629 ADDWF 0x29, F, ACCESS 0118 0E00 MOVLW 0x0 011A 222A ADDWFC 0x2A, F, ACCESS 011C 0E03 MOVLW 0x3 011E 2429 ADDWF 0x29, W, ACCESS 0120 6ED9 MOVWF FSR2, ACCESS 0122 0E00 MOVLW 0x0 0124 202A ADDWFC 0x2A, W, ACCESS 0126 6EDA MOVWF FSR2H, ACCESS 0128 C025 MOVFF 0x25, POSTINC2 012A FFDE NOP 012C C026 MOVFF 0x26, POSTDEC2 012E FFDD NOP 118: 119: // TODO same for PORTD when the steps board is printed 120: 121: // if the keypress flag is set, the main hasn't sent the packet (yet) 122: if (!(keypresses & (1<data_size; 03B4 EE20 LFSR 2, 0x1 03B6 F001 NOP 03B8 5161 MOVF pkt, W, BANKED 03BA 26D9 ADDWF FSR2, F, ACCESS 03BC 5162 MOVF c, W, BANKED 03BE 22DA ADDWFC FSR2H, F, ACCESS 03C0 CFDE MOVFF POSTINC2, pkt 03C2 F065 NOP 03C4 CFDD MOVFF POSTDEC2, p 03C6 F066 NOP 254: data = (uint8_t *) pkt->data; 03C8 0E03 MOVLW 0x3 03CA 2561 ADDWF pkt, W, BANKED 03CC 6F67 MOVWF channel, BANKED 03CE 0E00 MOVLW 0x0 03D0 2162 ADDWFC c, W, BANKED 03D2 6F68 MOVWF 0x68, BANKED 255: 256: putch((char)((pkt->status << 4) | pkt->channel)); 03D4 C061 MOVFF pkt, FSR2 03D6 FFD9 NOP 03D8 C062 MOVFF c, FSR2H 03DA FFDA NOP 03DC 38DF SWAPF INDF2, W, ACCESS 03DE 0B0F ANDLW 0xF 03E0 6F63 MOVWF 0x63, BANKED 03E2 C061 MOVFF pkt, FSR2 03E4 FFD9 NOP 03E6 C062 MOVFF c, FSR2H 03E8 FFDA NOP 03EA 50DF MOVF INDF2, W, ACCESS 03EC 0B0F ANDLW 0xF 03EE 6F64 MOVWF n, BANKED 03F0 3964 SWAPF n, W, BANKED 03F2 0BF0 ANDLW 0xF0 03F4 1163 IORWF 0x63, W, BANKED 03F6 ECDA CALL 0x5B4, 0 03F8 F002 NOP 257: 258: while (length--) { 03FA D00A BRA 0x410 259: putch((char) *(data++)); 03FC C067 MOVFF channel, FSR2 03FE FFD9 NOP 0400 C068 MOVFF 0x68, FSR2H 0402 FFDA NOP 0404 50DF MOVF INDF2, W, ACCESS 0406 ECDA CALL 0x5B4, 0 0408 F002 NOP 040A 0100 MOVLB 0x0 040C 4B67 INFSNZ channel, F, BANKED 040E 2B68 INCF 0x68, F, BANKED 260: } 0410 0100 MOVLB 0x0 0412 0765 DECF pkt, F, BANKED 0414 A0D8 BTFSS STATUS, 0, ACCESS 0416 0766 DECF p, F, BANKED 0418 2965 INCF pkt, W, BANKED 041A E1F0 BNZ 0x3FC 041C 2966 INCF p, W, BANKED 041E B4D8 BTFSC STATUS, 2, ACCESS 0420 0012 RETURN 0 0422 D7EC BRA 0x3FC 261: 262: return 0; 263: } --- C:/Program Files/Microchip/xc8/v1.44/sources/common/memset.c -------------------------------------- 1: #include 2: 3: #ifdef _PIC16 4: far void * 5: memset(far void * p1, int c, register size_t n) 6: #else /* _PIC16 */ 7: void * 8: memset(void * p1, int c, register size_t n) 9: #endif /* _PIC16 */ 10: { 11: 12: #ifdef _PIC16 13: register far char * p; 14: #else /* _PIC16 */ 15: register char * p; 16: #endif /* _PIC16 */ 17: 18: p = p1; 051A C060 MOVFF __pcstackBANK0, p 051C F066 NOP 051E C061 MOVFF pkt, channel 0520 F067 NOP 19: while(n--) 0522 D009 BRA 0x536 0536 0100 MOVLB 0x0 20: *p++ = c; 0524 C066 MOVFF p, FSR2 0526 FFD9 NOP 0528 C067 MOVFF channel, FSR2H 052A FFDA NOP 052C C062 MOVFF c, INDF2 052E FFDF NOP 0530 0100 MOVLB 0x0 0532 4B66 INFSNZ p, F, BANKED 0534 2B67 INCF channel, F, BANKED 0536 0100 MOVLB 0x0 0538 0764 DECF n, F, BANKED 053A A0D8 BTFSS STATUS, 0, ACCESS 053C 0765 DECF pkt, F, BANKED 053E 2964 INCF n, W, BANKED 0540 E1F1 BNZ 0x524 0542 2965 INCF pkt, W, BANKED 0544 B4D8 BTFSC STATUS, 2, ACCESS 0546 0012 RETURN 0 0548 D7ED BRA 0x524 21: return p1; 22: }