/* * File: main.c * Author: Naoki Pross 4E * Date: 08.01.2018 * Target: PIC18F44K22 * Version 1.0 * * Description: * * Main program for the Xylophone project. */ // PIC18F44K22 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config FOSC = INTIO7 // Oscillator Selection bits (Internal oscillator block) #pragma config PLLCFG = ON // 4X PLL Enable (Oscillator multiplied by 4) #pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal) // CONFIG2H #pragma config WDTEN = ON // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset) #pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status) #pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0) #pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2) #pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #define _XTAL_FREQ 64000000 #include "rs232.h" #include "midi.h" #include #include #include #include #include #define NOTES 15 #define NOTE_MASK 0xFF00 /* global variables */ volatile uint16_t keypresses[NOTES]; /* function prototypes */ int eusart_write_midi(const midi_message_t *pkt); /* interrupt service routine */ interrupt void isr(void) { unsigned char i, data; PORTDbits.RD3 = 0; if (PIR1bits.TMR2IF) { // PORTA data = PORTA; i = 7; do { keypresses[i] = (keypresses[i] << 1) | ((data >> i) & 0x01); } while (i--); data = PORTB; i = 7; do { keypresses[i] = (keypresses[i] << 1) | ((data >> i) & 0x01); } while (i-- - 8); // PORTB // for (i = 8; i < NOTES; i++) { // keypresses[i] = (keypresses[i] << 1) | ((PORTB & (1 << i)) >> i); // } // TODO same for PORTD when the steps board is printed // debug stuff PORTDbits.RD4 = PORTAbits.RA0; PORTDbits.RD2 = (keypresses[0] && !(keypresses[0] & NOTE_MASK)); // reset interrupt flag PIR1bits.TMR2IF = 0; } PORTDbits.RD3 = 1; } /* hardware configuration (inlined) */ inline void init_hw(void) { di(); /* PLL / FOSC configuration */ // enable PLL OSCTUNEbits.PLLEN = 1; // set FOSC to HFINTOSC (max frequency) OSCTUNEbits.TUN = 0b011111; // set 16 MHz oscillator, datasheet p.30 OSCCONbits.IRCF = 0b111; // select primary clock (with PLL) OSCCONbits.SCS = 0b00; /* i/o initializazion */ // disable all ADCs ANSELA = 0x00; ANSELB = 0x00; ANSELC = 0x00; ANSELD = 0x00; // TODO: remove demo TRISA = 0xFF; TRISB = 0xFF; TRISDbits.TRISD1 = 0; TRISDbits.TRISD2 = 0; TRISDbits.TRISD3 = 0; TRISDbits.TRISD4 = 0; // LED PORTDbits.RD1 = 1; // TEST OUTPUT 1 PORTDbits.RD2 = 0; // TEST OUTPUT 2 PORTDbits.RD3 = 1; // TEST OUTPUT 3 PORTDbits.RD4 = 0; /* timer configuration */ // timer 2 comp value PR2 = 128; // postscaler 1:4 T2CONbits.T2OUTPS = 0b0011; // prescaler 1:16 T2CONbits.T2CKPS = 0b11; // start timer T2CONbits.TMR2ON = 1; // timer 2 interrupts PIE1bits.TMR2IE = 1; PIR1bits.TMR2IF = 0; // enable peripheral interrupts INTCONbits.PEIE = 1; /* serial configuration */ eusart1_init(); ei(); } /* main program */ void main(void) { unsigned char i, data; midi_message_t sample_message; /* setup hardware */ init_hw(); /* setup software */ memset(keypresses, 0, sizeof(keypresses)); /* TODO remove demo code */ midi_note_on(&sample_message, 0x0, 0x3C, 0x7F); PORTDbits.RD1 = 0; /* main loop */ while (1) { eusart_write_midi(&sample_message); } } int eusart_write_midi(const midi_message_t *pkt) { size_t length; uint8_t *data; if (pkt == NULL) { return -1; } length = pkt->data_size; data = (uint8_t *) pkt->data; putch((char)((pkt->status << 4) | pkt->channel)); while (length--) { putch((char) *(data++)); } return 0; }