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| author | Nao Pross <naopross@thearcway.org> | 2017-06-16 13:57:39 +0200 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-06-16 13:57:39 +0200 |
| commit | 08fc6f3fd4461bfc78cd279809e1bf173e9f646e (patch) | |
| tree | 3194ab2330128c74e2a9ced876b526931358dd6a | |
| parent | merge branch 'hardware' (diff) | |
| parent | fixed typo in usart.h and in doc (diff) | |
| download | z80uPC-08fc6f3fd4461bfc78cd279809e1bf173e9f646e.tar.gz z80uPC-08fc6f3fd4461bfc78cd279809e1bf173e9f646e.zip | |
merge branch 'naopross'
merge to get the new doc on master
47 files changed, 2291 insertions, 430 deletions
diff --git a/doc/datasheets/M4-32_32-15JC.pdf b/doc/datasheets/M4-32_32-15JC.pdf Binary files differnew file mode 100644 index 0000000..7dcb44a --- /dev/null +++ b/doc/datasheets/M4-32_32-15JC.pdf diff --git a/doc/report/build.cmd b/doc/report/build.cmd deleted file mode 100644 index 3b4e8cd..0000000 --- a/doc/report/build.cmd +++ /dev/null @@ -1,4 +0,0 @@ -@echo off - - lualatex --output-directory=build notes.tex -pause
\ No newline at end of file diff --git a/doc/report/build/notes.pdf b/doc/report/build/notes.pdf Binary files differindex b0f0ec4..5a43c7d 100644 --- a/doc/report/build/notes.pdf +++ b/doc/report/build/notes.pdf diff --git a/doc/report/build/z80uPC.pdf b/doc/report/build/z80uPC.pdf Binary files differindex 38b7bcd..aff4174 100644 --- a/doc/report/build/z80uPC.pdf +++ b/doc/report/build/z80uPC.pdf diff --git a/doc/report/res/addrspace.pdf b/doc/report/res/addrspace.pdf Binary files differindex 2689fca..96ac657 100644 --- a/doc/report/res/addrspace.pdf +++ b/doc/report/res/addrspace.pdf diff --git a/doc/report/res/addrspace.svg b/doc/report/res/addrspace.svg index 6af7e7f..0f73784 100644 --- a/doc/report/res/addrspace.svg +++ b/doc/report/res/addrspace.svg @@ -9,12 +9,12 @@ xmlns="http://www.w3.org/2000/svg" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" - width="210mm" - height="297mm" - viewBox="0 0 210 297" + width="180.64061mm" + height="257.56342mm" + viewBox="0 0 180.64061 257.56342" version="1.1" id="svg8" - inkscape:version="0.92.0 r" + inkscape:version="0.92.1 r" sodipodi:docname="addrspace.svg"> <defs id="defs2" /> @@ -25,18 +25,22 @@ borderopacity="1.0" inkscape:pageopacity="0.0" inkscape:pageshadow="2" - inkscape:zoom="0.47482464" - inkscape:cx="396.85039" - inkscape:cy="477.01822" + inkscape:zoom="0.33575172" + inkscape:cx="902.43963" + inkscape:cy="551.46623" inkscape:document-units="mm" inkscape:current-layer="layer1" showgrid="false" showborder="false" - inkscape:window-width="1246" - inkscape:window-height="743" - inkscape:window-x="15" - inkscape:window-y="38" - inkscape:window-maximized="0" /> + inkscape:window-width="1266" + inkscape:window-height="763" + inkscape:window-x="5" + inkscape:window-y="28" + inkscape:window-maximized="0" + fit-margin-top="0" + fit-margin-left="0" + fit-margin-right="0" + fit-margin-bottom="0" /> <metadata id="metadata5"> <rdf:RDF> @@ -52,7 +56,8 @@ <g inkscape:label="Layer 1" inkscape:groupmode="layer" - id="layer1"> + id="layer1" + transform="translate(52.640604,-39.436588)"> <g id="g4712" transform="matrix(0.71111091,0,0,1.0012581,0,-0.3734815)"> @@ -82,78 +87,80 @@ </g> <text xml:space="preserve" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.87777778px;line-height:6.61458302px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.26458332;" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.05277824px;line-height:6.61458302px;font-family:'Roboto Mono';-inkscape-font-specification:'Roboto Mono, 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id="text4621"><tspan sodipodi:role="line" x="64.149452" y="236.76022" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.40555556px;line-height:15px;font-family:'Latin Modern Mono';-inkscape-font-specification:'Latin Modern Mono, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;writing-mode:lr;text-anchor:middle;stroke-width:0.26458332;" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.05277824px;line-height:15px;font-family:'Roboto Mono';-inkscape-font-specification:'Roboto Mono, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;writing-mode:lr-tb;text-anchor:middle;stroke-width:0.26458332" id="tspan4631">32KB RAM</tspan></text> <text xml:space="preserve" - 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id="text4621-8"><tspan @@ -167,7 +174,7 @@ y="147.85966">SPACE</tspan></text> <text xml:space="preserve" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.40555556px;line-height:15px;font-family:'Latin Modern Mono';-inkscape-font-specification:'Latin Modern Mono, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.26458332;" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.05277824px;line-height:15px;font-family:'Roboto Mono';-inkscape-font-specification:'Roboto Mono, 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differnew file mode 100755 index 0000000..b621307 --- /dev/null +++ b/doc/report/res/logo_sam.pdf diff --git a/doc/report/z80uPC.tex b/doc/report/z80uPC.tex index aa5d13c..eaad987 100644 --- a/doc/report/z80uPC.tex +++ b/doc/report/z80uPC.tex @@ -1,10 +1,299 @@ \documentclass[a4paper, 11pt, twoside]{article} +\usepackage{array} +\usepackage{float} +\usepackage{wrapfig} +% source code +\usepackage{listings} -\title{Z80 Single Board Computer Development} +% set correct hypenation +\usepackage[italian]{babel} + +% set margins +\usepackage[ + inner=2.5cm, + outer=2.5cm, + top=3cm, + bottom=3.75cm +]{geometry} + +% set headers +\usepackage{fancyhdr} +\pagestyle{fancyplain} +\fancyhf{} +\setlength{\headheight}{1.3cm} +\rhead{\includegraphics[height=1.25cm]{res/logo_sam}} +\lfoot{SAM 3E - Naoki Pross} +\rfoot{\thepage} + +% set font +\usepackage{fontspec} +\setmainfont{Roboto} +\setmonofont{Roboto Mono} + +% to fix macros +\usepackage{xspace} +% commands +% macro for project name +\newcommand{\prj}{Z80μPC\xspace} + +% invert signal (not, active low) +\newcommand{\inv}[1]{$\overline{\mbox{#1}}$} + +% metadata +\title{\vspace{-1cm}\texttt{\prj} Single Board \\ Computer Development } \author{Naoki Pross} +% document \begin{document} - \maketitle + +\maketitle +\begin{abstract} + Lo Zilog Z80 \`e un processore a 8 bit che fu introdotto nel 1976 che ebbe + un grandissimo successo nel mondo dell'elettronica e dell'informatica + nella fine del 20esimo secolo. In memoria di questo processore pioniere + dell'industria di sistemi embedded ho deciso di costruire un computer a + scopo generico intorno a questa piattaforma. L'obiettivo \`e di realizzare + una scheda programmabile con tutti i componenti necessari come ROM, RAM e + timers per far funzionare del software programmato se possibile sul + dispositivo stesso. +\end{abstract} + +\section{Specifiche tecniche dello Z80} +Lo Z80 \`e un processore molto minimalistico se paragonato a ci\`o che si +trova oggi sul mercato dei microcontrollori. Per il mio progetto ho deciso di +utilizzare il modello originale \texttt{Zilog Z8400} che non dispone di +sistemi integrati come i modelli SoC odierni. Le specifiche pi\`u importanti +sono elencate a seguire. + +\begin{itemize} + \item Architettura a 8 bit con bus a 16 bit con 64K indirizzi indirizzabili + \item Registri a 16 bit per {\tt SP,PC} e registri di utilizzo generico a + 8 bit {\tt A..F} combinabili a coppie {\tt AF,BC,..} per utilizzare + valori a 16 bit + \item Clock fino a 8 MHz + \item Segnali di controllo tra cui \texttt{\inv{RD}, \inv{WR}, + \inv{IOREQ}, \inv{MREQ}} e \texttt{\inv{RST}} + \item Interrupts mascherabili e non con vettore a 8 bit +\end{itemize} + +\section{Architettura di base} +Il minimo necessario per far funzionare un computer con lo Z80 sono una ROM e +una RAM, ma per il mio progetto ho scelto di aggiungere dell'hardware +aggiuntivo per lo sviluppo si sistemi pi\`u complessi per apprendere +conoscenze sia nel mondo dell'elettronica che dell'informatica. Per questa +ragione lo \prj possiede i seguienti componenti: + +\begin{center} +\begin{tabular}{ >{\tt}l >{\tt\bfseries}l p{.7\linewidth} } + % \hline \\ + ROM & M28C64 & EEPROM da 8KB x 8 bit (64K) per il BIOS / Bootloader / + OS installata doppia per avere 16KB \\ + RAM & HM62256B & SRAM da 32KB x 8bit (256K) \\ + CTC & Z8430 & Counter timer circuit ufficiale di Zilog a 4 canali che + permette di essere programmato \\ + PIO & Z8420 & Parallel input/output controller di Zilog per avere un + intefaccia digitale con due porte da 8 bit \\ + MMU & M4-32/32-15JC & CPLD programmabile che implementa una memory + management unit semplificata in grado di gestire i 5 + bit pi\`u significativi della linea di indirizzi \\ + USART & TL16C550C & Interfaccia USART per poter comunicare utilizzando il + protocollo RS232 +\end{tabular} +\end{center} + +Oltre a tutto ci\`o per uno scopo formativo lo \prj dispone anche di strumenti +da debug e analisi per comprendere ogni operazione del processore. Il modello +di Z80 scelto \`e in grado di utilizzare un clock fino a 8MHz, ma non +definisce un minimo dunque sono presenti 3 circuiti che generano 3 clock di +velocit\`a differenti. + +\begin{center} +\begin{tabular}{ >{\bfseries}r p{.8\linewidth} } + 0Hz & Questo clock \`e un bottone che permette di creare + manualmente le pulsazioni del clock, per poter analizzare + ogni istruzione \\ + 200Hz & Mediante un classico circuito con un LM555 si ha un clock da + 200Hz per eseguire i programmi a velocit\`a rallentata \\ + 4MHz & Clock per esecuzione a velocit\`a piena (normale) +\end{tabular} +\end{center} + +Una seconda disposizione per aiutare la comprensione del funzionamento del +processore \`e data da 6 display a 7 segmenti che durante l'esecuzione +rallentata o a step (bottone) visualizzano i bytes presenti sulla bus di +indirizzi a 16 bit e sul bus di dati a 8 bit. + +\begin{figure}[!h] \centering + \includegraphics[width=\linewidth]{res/bus_displays} + \caption{Display a 7 segmenti per visualizzare il flusso di dati della + CPU} +\end{figure} + +\section{Memory Management Unit} + +Alcuni modelli successori dello Z8400 implementavano una MMU SoC che +permetteva di indirizzare un address space di dimensione maggiore. Per lo \prj +non necessito di un indirizzamento pi\`u grande ma piuttosto sono interessato +dalle operazioni di gestione della memoria di una MMU simile a ci\`o che +accade nelle architetture X86. Nelle architetture odierne basate sull'X86/64 +\`e presente un sistema di traslazione di indirizzi di memoria da virtuale a +fisica. Con lo scopo di trarne solamente i vantaggi pi\`u fondamentali lo \prj +implementa nella CPLD MMU un sistema basilare di gestione di pagine di memoria +con traslazione di indirizzi in modo da poter allocare pi\`u programmi nella +RAM anche se il sistema non implementa il multitasking. + +% TODO: write about this in more details + +\subsection{Address Space} + +\begin{wrapfigure}{r}{.4\linewidth} \centering + \vspace{8mm} + \includegraphics[width=.9\linewidth]{res/addrspace} + \vspace{4mm} + \caption{Address space dello \prj} +\end{wrapfigure} +La funzione primaria della MMU \`e di mappare i dispositivi I/O e le memorie +nell'address space. Nell'implementazione reale la MMU controlla i segnali {\tt +\inv{CS}} seguendo una logica combinatoria molto semplice che controlla se +l'indirizzo sul bus si trova in una zona definita per un dispositivo. +L'address space si presenta dunque nella seguente maniera, per cui la ROM +occupa il primo quarto, i dispositivi mappabili il secondo quarto e la RAM la +met\`a restante. Essendo un progetto pensato per essere esteso 16KB sono +liberi per mappare dispositivi esterni collegati attraverso il connettore +DIN41612. + +% \begin{wrapfigure}{l}{.4\linewidth} \centering +% \includegraphics[width=.8\linewidth]{res/iospace} +% \end{wrapfigure} + +\subsection{Page Table} + +Per poter controllare la traslazione degli indirizzi la MMU dispone di una +Page Table a cui \`e possibile accedere attraversso un certo indirizzo +nell'I/O space. La page table di 5 bit permette la gestione delle regioni di +memoria da impostare per dei determinati processi. Questa funzione \`e +importante perch\`e permette la separazione dello stack e della memoria della +kernel dai programmi normali. Per lo \prj potrebbe sembrare eccessivo ma +essendo uno strumento per apprendere le fondamenta dell'elettronica e +dell'informatica \`e interessante implementare questa funzionalit\`a che +comunque se necessario pu\`o essere disabilitata. + +\section{Schema a blocchi} + +\begin{figure}[!h] \centering + \includegraphics[width=.85\linewidth]{res/block_diagram} +\end{figure} + +\section{Software / Sistema operativo} + +Negli sviluppi pi\`u recenti intorno allo Z80 esso veniva utilizzato come un +microcontrollore anzich\`e come processore da computer, per questa ragione non +sono presenti molti sistemi operativi per questa piattaforma. Dunque per lo +\prj il progetti implementa un sistema operativo soprannominato {\tt +HelvetiOS} con le funzioni minime necessarie come un interfaccia seriale a +comandi e un meccanismo per caricare i programmi. + +\subsection{Componenti di base} + +Per garantire un funzionamento minimo il sistema {\tt HelvetiOS} deve offrire +drivers e utility di base quali: + +\begin{center} +\begin{minipage}[t]{.4\linewidth} + \begin{itemize} + \item USART driver and API + \item PIO driver and API + \item CTC driver and API + \end{itemize} +\end{minipage}% +\begin{minipage}[t]{.4\linewidth} + \begin{itemize} + \item Bootloader + \item Program launcher + \item Shell-like interface + \end{itemize} +\end{minipage} +\end{center} + +\subsection{Interfacce dell'API} + +Nel corso dello sviluppo questa sezione verr\`a continuamente espansa per +documentare le interfacce dei vari drivers. + +\subsubsection{USART} +\begin{lstlisting}[language=C, basicstyle=\ttfamily] +void usart_set_baudrate(uint16_t baudrate); +void usart_set_parity(int mode); +void usart_set_stop_bits(int count); +void usart_set_word_length(int length); +void usart_set_autoflow(int mode); + +inline void usart_init(uint16_t baudrate, int parity, int stop_bits); + +void usart_transmit(uint8_t data); +uint8_t usart_receive(); + +int usart_write(uint8_t *data, size_t size); +int usart_read(uint8_t *buffer, size_t count); +\end{lstlisting} + +% \subsection{PIO} + +\subsection{Toolchain per la compilazione} + +Per compilare il software del progetto si utilizza SDCC, un progetto +open-source che supporta la compilazione di binari per l'architettura dello +Z80. Nella mia configurazione utilizzo GNU make con il seguente makefile. + +\newpage +\begin{lstlisting}[language=make, numbers=left, basicstyle=\ttfamily] +#### +# Source code settings +# +OSNAME := helvetiOS + +CSOURCES := $(wildcard kernel/*.c) $(wildcard libc/*.c) +OBJECTS := $(patsubst %.c,build/%.rel,$(CSOURCES)) +HEXFILE := build/$(OSNAME).hex +BINARY := build/$(OSNAME).bin + +### +# Compiler settings + +CC := sdcc + +CFLAGS := -mz80 \ + -I kernel/include -I libc/include -DDEBUG + +LDFLAGS := -mz80 --no-std-crt0 crt0.rel \ + --code-loc 0x0800 --data-loc 0x8000 + +.PHONY: dirs dis clean +all: $(BINARY) + +# build binary +$(BINARY): $(OBJECTS) dirs + $(CC) $(LDFLAGS) $(OBJECTS) -o $(HEXFILE) + xxd -r -p $(HEXFILE) $(BINARY) + +$(OBJECTS): build/%.rel : %.c $(CSOURCES) dirs crt0.rel + $(CC) $(CFLAGS) -c $< -o $@ + +crt0.rel: crt0.s + sdasz80 -o $< + +dirs: + mkdir -p build build/kernel build/libc + +dis: $(BINARY) + z80dasm -a -g 0h $< -o $(OSNAME).s + +clean: + - rm -rd build/* + - rm $(OSNAME).s + - rm crt0.rel +\end{lstlisting} + \end{document} diff --git a/sw/cpld/ADDRESS_DECODER.STY b/sw/cpld/ADDRESS_DECODER.STY new file mode 100644 index 0000000..afd24c5 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.STY @@ -0,0 +1,4 @@ +[STRATEGY-LIST] +Normal=True, 1491209776 +[synthesis-type] +tool=Synplify diff --git a/sw/cpld/ADDRESS_DECODER.lci b/sw/cpld/ADDRESS_DECODER.lci new file mode 100644 index 0000000..47875d5 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.lci @@ -0,0 +1,107 @@ + +[Device] +Family = M4A3; +PartNumber = M4A3-32/32-10JC; +Package = 44PLCC; +PartType = M4A3-32/32; +Speed = -10; +Operating_condition = COM; +Status = Production; + +[Revision] +Parent = m4a332.lci; +DATE = 2002; +TIME = 0:00:00; +Source_Format = Pure_VHDL; +Synthesis = Synplify; + +[Ignore Assignments] + +[Clear Assignments] + +[Backannotate Assignments] + +[Global Constraints] + +[Location Assignments] +layer = OFF; + +[Group Assignments] +layer = OFF; + +[Resource Reservations] +layer = OFF; + +[Fitter Report Format] + +[Power] + +[Source Constraint Option] + +[Fast Bypass] + +[OSM Bypass] + +[Input Registers] + +[Netlist/Delay Format] +NetList = VHDL; + +[IO Types] +layer = OFF; + +[Pullup] + +[Slewrate] + +[Region] + +[Timing Constraints] + +[HSI Attributes] + +[Input Delay] + +[opt global constraints list] + +[Explorer User Settings] + +[Pin attributes list] + +[global constraints list] + +[Global Constraints Process Update] + +[pin lock limitation] + +[LOCATION ASSIGNMENTS LIST] + +[RESOURCE RESERVATIONS LIST] + +[individual constraints list] + +[Attributes list setting] + +[Timing Analyzer] + +[PLL Assignments] + +[Dual Function Macrocell] + +[Explorer Results] + +[VHDL synplify constraints] + +[VHDL spectrum constraints] + +[verilog synplify constraints] + +[verilog spectrum constraints] + +[VHDL synplify constraints list] + +[VHDL spectrum constraints list] + +[verilog synplify constraints list] + +[verilog spectrum constraints list] diff --git a/sw/cpld/ADDRESS_DECODER.lct b/sw/cpld/ADDRESS_DECODER.lct new file mode 100644 index 0000000..47875d5 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.lct @@ -0,0 +1,107 @@ + +[Device] +Family = M4A3; +PartNumber = M4A3-32/32-10JC; +Package = 44PLCC; +PartType = M4A3-32/32; +Speed = -10; +Operating_condition = COM; +Status = Production; + +[Revision] +Parent = m4a332.lci; +DATE = 2002; +TIME = 0:00:00; +Source_Format = Pure_VHDL; +Synthesis = Synplify; + +[Ignore Assignments] + +[Clear Assignments] + +[Backannotate Assignments] + +[Global Constraints] + +[Location Assignments] +layer = OFF; + +[Group Assignments] +layer = OFF; + +[Resource Reservations] +layer = OFF; + +[Fitter Report Format] + +[Power] + +[Source Constraint Option] + +[Fast Bypass] + +[OSM Bypass] + +[Input Registers] + +[Netlist/Delay Format] +NetList = VHDL; + +[IO Types] +layer = OFF; + +[Pullup] + +[Slewrate] + +[Region] + +[Timing Constraints] + +[HSI Attributes] + +[Input Delay] + +[opt global constraints list] + +[Explorer User Settings] + +[Pin attributes list] + +[global constraints list] + +[Global Constraints Process Update] + +[pin lock limitation] + +[LOCATION ASSIGNMENTS LIST] + +[RESOURCE RESERVATIONS LIST] + +[individual constraints list] + +[Attributes list setting] + +[Timing Analyzer] + +[PLL Assignments] + +[Dual Function Macrocell] + +[Explorer Results] + +[VHDL synplify constraints] + +[VHDL spectrum constraints] + +[verilog synplify constraints] + +[verilog spectrum constraints] + +[VHDL synplify constraints list] + +[VHDL spectrum constraints list] + +[verilog synplify constraints list] + +[verilog spectrum constraints list] diff --git a/sw/cpld/ADDRESS_DECODER.naf b/sw/cpld/ADDRESS_DECODER.naf new file mode 100644 index 0000000..fe52855 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.naf @@ -0,0 +1,22 @@ +PA[15] i +PA[14] i +PA[13] i +PA[12] i +PA[11] i +PA[10] i +PA[9] i +PA[8] i +PA[7] i +PA[6] i +PA[5] i +PA[4] i +PA[3] i +PA[2] i +PA[1] i +PA[0] i +CSROMH o +CSROML o +CSRAM o +CSUART o +CSCTC o +CSPIO o diff --git a/sw/cpld/ADDRESS_DECODER.syn b/sw/cpld/ADDRESS_DECODER.syn new file mode 100644 index 0000000..419b6ba --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.syn @@ -0,0 +1,11 @@ +JDF B +// Created by Version 2.0 +PROJECT ADDRESS_DECODER +DESIGN address_decoder Normal +DEVKIT M4A3-32/32-10JC +ENTRY Pure VHDL +MODULE address_decoder.vhd +MODSTYLE ADDRESS_DECODER Normal +SYNTHESIS_TOOL Synplify +SIMULATOR_TOOL ActiveHDL +TOPMODULE ADDRESS_DECODER diff --git a/sw/cpld/ADDRESS_DECODER.tcl b/sw/cpld/ADDRESS_DECODER.tcl new file mode 100644 index 0000000..4c9fe3f --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.tcl @@ -0,0 +1,270 @@ + +########## Tcl recorder starts at 04/03/17 14:05:56 ########## + +set version "2.0" +set proj_dir "//nas001/account_PIF/_prossn/SAMB_3/lab3/projects/z80uPC/sw/cpld" +cd $proj_dir + +# Get directory paths +set pver $version +regsub -all {\.} $pver {_} pver +set lscfile "lsc_" +append lscfile $pver ".ini" +set lsvini_dir [lindex [array get env LSC_INI_PATH] 1] +set lsvini_path [file join $lsvini_dir $lscfile] +if {[catch {set fid [open $lsvini_path]} msg]} { + puts "File Open Error: $lsvini_path" + return false +} else {set data [read $fid]; close $fid } +foreach line [split $data '\n'] { + set lline [string tolower $line] + set lline [string trim $lline] + if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue} + if {$path && [regexp {^\[} $lline]} {set path 0; break} + if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue} + if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue} + if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}} + +set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end] +regsub -all "\"" $cpld_bin "" cpld_bin +set cpld_bin [file join $cpld_bin] +set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]] +regsub -all "\"" $install_dir "" install_dir +set install_dir [file join $install_dir] +set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end] +regsub -all "\"" $fpga_dir "" fpga_dir +set fpga_dir [file join $fpga_dir] +set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end] +regsub -all "\"" $fpga_bin "" fpga_bin +set fpga_bin [file join $fpga_bin] + +if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } { + set env(PATH) "$fpga_bin;$env(PATH)" } + +if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } { + set env(PATH) "$cpld_bin;$env(PATH)" } + +lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"] +package require runcmd + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:05:56 ########### + + +########## Tcl recorder starts at 04/03/17 14:07:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:07:59 ########### + + +########## Tcl recorder starts at 04/03/17 14:08:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:08:48 ########### + + +########## Tcl recorder starts at 04/03/17 14:11:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:11:44 ########### + + +########## Tcl recorder starts at 04/03/17 14:22:22 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:22:22 ########### + + +########## Tcl recorder starts at 04/03/17 14:22:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:22:31 ########### + + +########## Tcl recorder starts at 04/03/17 14:28:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:28:11 ########### + + +########## Tcl recorder starts at 04/03/17 14:56:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:56:18 ########### + + +########## Tcl recorder starts at 04/03/17 14:56:23 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/03/17 14:56:23 ########### + + +########## Tcl recorder starts at 04/13/17 10:29:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/13/17 10:29:16 ########### + + +########## Tcl recorder starts at 04/13/17 10:29:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/13/17 10:29:50 ########### + + +########## Tcl recorder starts at 04/13/17 10:33:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/13/17 10:33:10 ########### + + +########## Tcl recorder starts at 04/13/17 10:33:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/13/17 10:33:11 ########### + + +########## Tcl recorder starts at 04/13/17 10:34:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/13/17 10:34:43 ########### + diff --git a/sw/cpld/ADDRESS_DECODER_tcl.ini b/sw/cpld/ADDRESS_DECODER_tcl.ini new file mode 100644 index 0000000..fae7b5f --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER_tcl.ini @@ -0,0 +1,5 @@ +[Tcl] +Start = Yes; +Process = YES; +Append = YES; +TclFilename = ADDRESS_DECODER.tcl; diff --git a/sw/cpld/address_decoder.jhd b/sw/cpld/address_decoder.jhd new file mode 100644 index 0000000..19ef983 --- /dev/null +++ b/sw/cpld/address_decoder.jhd @@ -0,0 +1,3 @@ + + +MODULE ADDRESS_DECODER diff --git a/sw/cpld/address_decoder.jid b/sw/cpld/address_decoder.jid new file mode 100644 index 0000000..f0d5286 --- /dev/null +++ b/sw/cpld/address_decoder.jid @@ -0,0 +1 @@ +. ADDRESS_DECODER address_decoder.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld\address_decoder.vhd diff --git a/sw/cpld/address_decoder.rev b/sw/cpld/address_decoder.rev new file mode 100644 index 0000000..e8bfb3d --- /dev/null +++ b/sw/cpld/address_decoder.rev @@ -0,0 +1,3 @@ +<SYNPROJ_Revision_Control> +<RevisionControl_Info/> +</SYNPROJ_Revision_Control> diff --git a/sw/cpld/address_decoder.vhd b/sw/cpld/address_decoder.vhd new file mode 100644 index 0000000..2c80f86 --- /dev/null +++ b/sw/cpld/address_decoder.vhd @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity ADDRESS_DECODER is + +port( + -- address input + PA: in unsigned(15 downto 0); + + -- chip selects output + -- memory + CSROMH: out std_logic; + CSROML: out std_logic; + CSRAM : out std_logic; + -- io chips + CSUART: out std_logic; + CSCTC : out std_logic; + CSPIO : out std_logic +); + +end; + +architecture Behavioral of ADDRESS_DECODER is +begin + -- memory + CSROMH <= 0 when ((PA >= x"0000") and (PA < x"2000")); + CSROML <= 0 when ((PA >= x"4000") and (PA < x"4000")); + CSRAM <= 0 when (PA >= x"D000"); + -- io chips + CSUART <= 0 when ((PA >= x"4000") and (PA < x"4008")); + -- CSCTC + -- CSPIO + +end Behavioral; + diff --git a/sw/cpld/automake.log b/sw/cpld/automake.log new file mode 100644 index 0000000..f24e14f --- /dev/null +++ b/sw/cpld/automake.log @@ -0,0 +1,10 @@ +ispLEVER Auto-Make Log File +--------------------------- + +Updating: Hierarchy +Start to record tcl script... +Finished recording TCL script. + +Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\vhd2jhd.exe address_decoder.vhd -o address_decoder.jhd -m "C:\ispLEVER_Classic2\ispcpld/generic/lib/vhd/location.map" -p "C:\ispLEVER_Classic2\ispcpld/generic/lib"' + +Done: completed successfully. diff --git a/sw/cpld/syndos.env b/sw/cpld/syndos.env new file mode 100644 index 0000000..16036da --- /dev/null +++ b/sw/cpld/syndos.env @@ -0,0 +1,41 @@ +ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5 +DIOEDA_ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5 +DIOEDA_ActiveHDL=C:\ispLEVER_Classic2\active-hdl\BIN +DIOEDA_ActiveHDLPath=C:\ispLEVER_Classic2\active-hdl\BIN +DIOEDA_AppNotes=C:\ispLEVER_Classic2\ispcpld\bin +DIOEDA_Bin=C:\ispLEVER_Classic2\ispcpld\bin +DIOEDA_Config=C:\ispLEVER_Classic2\ispcpld\config +DIOEDA_CONTEXT=ispLEVER CLASSIC +DIOEDA_DSPPATH=C:\ispLEVER_Classic2\ispLeverDSP +DIOEDA_EPICPATH=C:\ispLEVER_Classic2\ispfpga\bin\nt +DIOEDA_Examples=C:\ispLEVER_Classic2\examples +DIOEDA_FPGABinPath=C:\ispLEVER_Classic2\ispfpga\bin\nt +DIOEDA_FPGAPath=C:\ispLEVER_Classic2\ispfpga +DIOEDA_HDLExplorer=C:\ispLEVER_Classic2\hdle\win32 +DIOEDA_INI=C:\lsc_env +DIOEDA_ispVM=C:\ispLEVER_Classic2\ispvmsystem +DIOEDA_ispVMSystem=C:\ispLEVER_Classic2\ispvmsystem +DIOEDA_License=C:\ispLEVER_Classic2\license +DIOEDA_LSEPath=C:\ispLEVER_Classic2\lse +DIOEDA_MachPath=C:\ispLEVER_Classic2\ispcpld\bin +DIOEDA_Manuals=C:\ispLEVER_Classic2\ispcpld\manuals +DIOEDA_ModelSim=C:\ispLEVER_Classic2\modelsim\win32loem +DIOEDA_ModelsimPath=C:\ispLEVER_Classic2\modelsim\win32loem +DIOEDA_PDSPath=C:\ispLEVER_Classic2\ispcomp +DIOEDA_Precision=C:\isptools\precision +DIOEDA_PrecisionPath=C:\isptools\precision +DIOEDA_ProductName=ispLEVER +DIOEDA_ProductPrefix=SYN +DIOEDA_ProductTitle=ispLEVER +DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N +DIOEDA_ProductVersion=2.0.00.17 +DIOEDA_ProgramFolder=ispLEVER Classic 2.0 +DIOEDA_Root=C:\ispLEVER_Classic2\ispcpld +DIOEDA_Spectrum=C:\isptools\spectrum +DIOEDA_SpectrumPath=C:\isptools\spectrum +DIOEDA_Synplify=C:\ispLEVER_Classic2\synpbase +DIOEDA_SynplifyPath=C:\ispLEVER_Classic2\synpbase +DIOEDA_Synthesis=C:\ispLEVER_Classic2\lse\bin\nt +DIOEDA_Tutorial=C:\ispLEVER_Classic2\ispcpld\tutorial +DIOPRODUCT=ispLEVER +PATH=C:\ispLEVER_Classic2\ispcpld\bin diff --git a/sw/pld/ADDRESS_DECODER.abs b/sw/pld/ADDRESS_DECODER.abs Binary files differdeleted file mode 100644 index ab6deb9..0000000 --- a/sw/pld/ADDRESS_DECODER.abs +++ /dev/null diff --git a/sw/pld/ADDRESS_DECODER.jed b/sw/pld/ADDRESS_DECODER.jed deleted file mode 100644 index 0525a9d..0000000 --- a/sw/pld/ADDRESS_DECODER.jed +++ /dev/null @@ -1,28 +0,0 @@ - -CUPL(WM) 5.0a Serial# 60008009 -Device g16v8as Library DLIB-h-40-2 -Created Fri Mar 17 15:18:30 2017 -Name ADDRESS_DECODER -Partno 00 -Revision 01 -Date 17.03.2017 -Designer Engineer -Company SAM Bellinzona -Assembly None -Location -*QP20 -*QF2194 -*G0 -*F0 -*L00512 01110111101110111011011110111011 -*L00768 10110111101110111011011110111011 -*L01024 10111011101110111011011110111011 -*L01280 11111111111111111111111111111011 -*L01536 11111111111111111111011110111011 -*L01792 11111111111111111111101110111011 -*L02048 00000100001100000011000000100000 -*L02112 00000000110000001111111111111111 -*L02144 11111111111111111111111111111111 -*L02176 111111111111111110 -*C1E45 -*A086
\ No newline at end of file diff --git a/sw/pld/ADDRESS_DECODER.pdf b/sw/pld/ADDRESS_DECODER.pdf deleted file mode 100644 index 2a0c7dc..0000000 --- a/sw/pld/ADDRESS_DECODER.pdf +++ /dev/null @@ -1,169 +0,0 @@ -{COMPONENT F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER.SYM - - {ENVIRONMENT - {PDIFvrev 3.00} - {Program "CUPL(WM) Version 5.0a"} - {DBtype "Schematic"} - {DBvrev 1.01} - {DBtime "Fri Mar 17 15:18:30 2017 "} - {DBunit "MIL"} - {DBgrid 10} - {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 - "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 - "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 - "CMPNAM" 5 "BORDER" 5} - } - - {USER - {VIEW - {Mode SYMB} - {Nlst OPEN} - {Vw 0 0 2} - {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0} - {Gs 10 10} - } - } - - {DISPLAY - [Ly "PINNUM"] - [Ls "SOLID"][Wd 0] - [Ts 15][Tj "LC"][Tr 0][Tm "N"] - } - - {SYMBOL - {PIN_DEF - [Ly "PINCON"] - {P A8 {Pt "INPUT"}{Lq 0}{Ploc 100 160}} - {P A9 {Pt "INPUT"}{Lq 0}{Ploc 100 140}} - {P A10 {Pt "INPUT"}{Lq 0}{Ploc 100 120}} - {P A11 {Pt "INPUT"}{Lq 0}{Ploc 100 100}} - {P A12 {Pt "INPUT"}{Lq 0}{Ploc 100 80}} - {P A13 {Pt "INPUT"}{Lq 0}{Ploc 100 60}} - {P A14 {Pt "INPUT"}{Lq 0}{Ploc 100 40}} - {P A15 {Pt "INPUT"}{Lq 0}{Ploc 100 20}} - {P CSROML {Pt "I/O"}{Lq 0}{Ploc 290 20}} - {P CSROMH {Pt "I/O"}{Lq 0}{Ploc 290 40}} - {P CSRAM {Pt "I/O"}{Lq 0}{Ploc 290 60}} - {P CSUART {Pt "I/O"}{Lq 0}{Ploc 290 80}} - {P CSCTC {Pt "I/O"}{Lq 0}{Ploc 290 100}} - {P CSPIO {Pt "I/O"}{Lq 0}{Ploc 290 120}} - } - - {PKG - [Ly "REFDES"] - [Ts 25][Tj "CB"][Tr 0][Tm "N"] - {Rdl 195 190} - - [Ly "PINNUM"] - [Ts 15][Tj "RC"] - {Pnl 120 170} - {Pnl 120 150} - {Pnl 120 130} - {Pnl 120 110} - {Pnl 120 90} - {Pnl 120 70} - {Pnl 120 50} - {Pnl 120 30} - [Ts 15][Tj "LC"] - {Pnl 270 30} - {Pnl 270 50} - {Pnl 270 70} - {Pnl 270 90} - {Pnl 270 110} - {Pnl 270 130} - - {Sd A 2 3 4 5 6 7 8 9 12 13 14 15 16 17} - } - - {PIC - [Ly "GATE"] - [Ts 15][Tj "LC"][Tr 0][Tm "N"] - {R 130 180 260 0} - {L 130 160 100 160} - {L 130 140 100 140} - {L 130 120 100 120} - {L 130 100 100 100} - {L 130 80 100 80} - {L 130 60 100 60} - {L 130 40 100 40} - {L 130 20 100 20} - {L 260 20 290 20} - {L 260 40 290 40} - {L 260 60 290 60} - {L 260 80 290 80} - {L 260 100 290 100} - {L 260 120 290 120} - [Ly "PINNAM"] - [Tj "LC"] - {T "A8" 140 160} - {T "A9" 140 140} - {T "A10" 140 120} - {T "A11" 140 100} - {T "A12" 140 80} - {T "A13" 140 60} - {T "A14" 140 40} - {T "A15" 140 20} - [Tj "RC"] - {T "CSROML" 250 20} - {T "CSROMH" 250 40} - {T "CSRAM" 250 60} - {T "CSUART" 250 80} - {T "CSCTC" 250 100} - {T "CSPIO" 250 120} - [Ly "DEVICE"] - [Tj "CT"] - {T "G16V8AS" 195 -10} - } - - {ATR - {IN - {Org 100 20} - {Ty 255} - } - {EX - [Ly "ATTR2"] - [Ts 12][Tj "CT"][Tr 0][Tm "N"] - {At PLD F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER 195 180} - } - } - } - - {DETAIL - {ANNOTATE - } - - {NET_DEF - {N A8 - } - {N A9 - } - {N A10 - } - {N A11 - } - {N A12 - } - {N A13 - } - {N A14 - } - {N A15 - } - {N CSROML - } - {N CSROMH - } - {N CSRAM - } - {N CSUART - } - {N CSCTC - } - {N CSPIO - } - } - - {SUBCOMP - } - } -} diff --git a/sw/pld/ADDRESS_DECODER.sim b/sw/pld/ADDRESS_DECODER.sim deleted file mode 100644 index 05661c0..0000000 --- a/sw/pld/ADDRESS_DECODER.sim +++ /dev/null @@ -1,50 +0,0 @@ -%SIGNAL -PIN 2 = A8 -PIN 3 = A9 -PIN 4 = A10 -PIN 5 = A11 -PIN 6 = A12 -PIN 7 = A13 -PIN 8 = A14 -PIN 9 = A15 -PIN 16 = CSCTC -PIN 17 = CSPIO -PIN 14 = CSRAM -PIN 13 = CSROMH -PIN 12 = CSROML -PIN 15 = CSUART -%END - -%FIELD -%END - -%EQUATION -CSCTC => - !A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15 - -CSPIO => - A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15 - -CSRAM => - !A15 - -CSROMH => - A13 & !A14 & !A15 - -CSROML => - !A13 & !A14 & !A15 - -CSTIMER => - A15 - # A14 - # !A13 - # A12 - # A11 - # A10 - # A9 - # !A8 - -CSUART => - !A8 & !A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15 - -%END diff --git a/sw/pld/__Previews/ADDRESS DECODER.PLDPreview b/sw/pld/__Previews/ADDRESS DECODER.PLDPreview deleted file mode 100644 index 8b8cb8c..0000000 --- a/sw/pld/__Previews/ADDRESS DECODER.PLDPreview +++ /dev/null @@ -1,14 +0,0 @@ -[Preview] -LargeImageOriginalSize=708000 -LargeImageWidth=354 -LargeImageHeight=500 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- diff --git a/sw/pld/address_decoder.PLD b/sw/pld/address_decoder.PLD deleted file mode 100644 index 1cc9e22..0000000 --- a/sw/pld/address_decoder.PLD +++ /dev/null @@ -1,35 +0,0 @@ -Name ADDRESS_DECODER ; -PartNo 00 ; -Date 17.03.2017 ; -Revision 01 ; -Designer Engineer ; -Company SAM Bellinzona ; -Assembly None ; -Location ; -Device g16v8a; - -/* *************** INPUT PINS *********************/ -PIN 2 = A8 ; -PIN 3 = A9 ; -PIN 4 = A10 ; -PIN 5 = A11 ; -PIN 6 = A12 ; -PIN 7 = A13 ; -PIN 8 = A14 ; -PIN 9 = A15 ; - -/* *************** OUTPUT PINS *********************/ -PIN 12 = CSROML ; -PIN 13 = CSROMH ; -PIN 14 = CSRAM ; -PIN 15 = CSUART ; -PIN 16 = CSCTC ; -PIN 17 = CSPIO ; - -CSRAM = !A15 ; -CSROML = !(!A15 & !A14 & !A13) ; -CSROMH = !(!A15 & !A14 & A13) ; -CSUART = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & !A9 & !A8) ; -CSTIMER = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & !A9 & A8) ; -CSCTC = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & A9 & !A8) ; -CSPIO = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & A9 & A8) ; diff --git a/sw/z80/coding_rules.txt b/sw/z80/coding_rules.txt new file mode 100644 index 0000000..e5c11f0 --- /dev/null +++ b/sw/z80/coding_rules.txt @@ -0,0 +1,120 @@ +CODING STYLE FOR THIS PROJECT +============================= + +In order to have a consistent codebase, there are the following rules on +writing code in C (and assembly). For the most part they are similar to the +Linux kernel coding rules by Torvalds. + +PROGRAM LOGIC +------------- +I expect a certain level of common sense from people so I won't mention the +super-basic stuff. But I would like to point out a few thing I WON'T accept +(unless there is a valid reason and an explanation of why). First, I believe +that code has to be aesthetically pleasing to watch and with a clear logic +flow so: + + - Avoid deeply nested code and recursive black magic + + - No special cases: generally the code of a function should behave the + same with any argument. Avoid horrible exceptions for magic values + + - No extreme modularization: do not write code that is extremely + encapsulated with dozens of helper functions to control every signal + that runs through the damn motherboard + +EDITOR (SPACES > TABS) +---------------------- +You can use your favourite editor but spaces are better than tabs, no +discussion. For this project every source file must have an indent of 4 +spaces. Since 80 characters is the standard terminal width, the code has to be +hard wrapped at 80, 78 or 72 characters. Also there shouldn't be any markup on +the source code for your editor, not even in the comments; just the code. + + - use spaces, 1 indent - 4 spaces + - hard wrap at 80 / 78 / 72 characters + - no markup for folds or any other editor specific feature + + +C CODE INDENT AND BRACES +------------------------ +I personally prefer the K&R coding style because it was used in 'The C +Programming Language' book from Dennis Ritchie which is the 'standard' for +learning C. But I also like Linus' kernel coding rules, so sometimes I might +use some of his rules. Anyway, you can look them up if you want to or just +look at the following example that sums most of the important stuff. + + - K&R braces and function prototypes + - snake_case for variables and function names + - pointer asterisk in front of the variable ( ex: int *p; ) + +Here's a short example that uses most of the stuff: + + #include <stdio.h> + #include <stdlib.h> + + #define MY_DEVICE_MEMORY_ADDR 0x5020 + + #define MY_DEVICE_FLAG_RDY 1 + #define MY_DEVICE_FLAG_ERR 2 + + // same for unions + struct my_device + { + volatile uint8_t buffer; + volatile uint8_t flags; + } *_my_dev = (struct my_device *) MY_DEVICE_MEMORY_ADDR; + + + int my_device_write(uint8_t *data, size_t size); + + /* This is the main function + * and this is a multiline comment to explain something if needed + */ + int main(int argc, char *argv[]) + { + int i; + int j = 0; + uint8_t data[2] = { 0xFF, 0xAB }; + const char *string = "My magic string"; + + while (j < 100) { + j++; + } + + printf("%s\n", string); + + if (some_condition) { + // inline comment + } else { + my_device_write(data, 2); + } + + switch (i) { + case 0: + some_function(); + break; + + case 1: + // ... + break; + + default: + // ... + } + } + + int my_device_write(uint8_t *data, size_t size) + { + int i; + + for (i = 0; i < size; i++) { + _my_dev.buffer = data; + while (!(_my_dev.flags & (1<<MY_DEVICE_FLAG_RDY))); + + if (_my_dev.flags & (1<<MY_DEVICE_FLAG_ERR)) { + return -1; + } + } + + return i; + } diff --git a/sw/z80/crt0.s b/sw/z80/crt0.s index d0ae3ca..00c7da1 100644 --- a/sw/z80/crt0.s +++ b/sw/z80/crt0.s @@ -1,30 +1,103 @@ - .area _HEADER (ABS) - ;; reset vector - .org 0 - jp init - - .org 0x08 - reti - .org 0x10 - reti - .org 0x18 - reti - .org 0x20 - reti - .org 0x28 - reti - .org 0x30 - reti - .org 0x38 - reti - - .org 0x100 +;-------------------------------------------------------------------------- +; crt0.s - Generic crt0.s for a Z80 +; +; Copyright (C) 2000, Michael Hope +; +; This library is free software; you can redistribute it and/or modify it +; under the terms of the GNU General Public License as published by the +; Free Software Foundation; either version 2, or (at your option) any +; later version. +; +; This library is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this library; see the file COPYING. If not, write to the +; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +; MA 02110-1301, USA. +; +; As a special exception, if you link this library with other files, +; some of which are compiled with SDCC, to produce an executable, +; this library does not by itself cause the resulting executable to +; be covered by the GNU General Public License. This exception does +; not however invalidate any other reasons why the executable file +; might be covered by the GNU General Public License. +;-------------------------------------------------------------------------- + .module crt0 + .globl _kmain + + .area _HEADER (ABS) + ;; Reset vector + .org 0 + jp init + + .org 0x08 + reti + .org 0x10 + reti + .org 0x18 + reti + .org 0x20 + reti + .org 0x28 + reti + .org 0x30 + reti + .org 0x38 + reti + + .org 0x100 init: - ;; set stack - ld sp,#0xFFFF + ;; Set stack pointer directly above top of memory. + ld sp,#0xFFFF + + ;; Initialise global variables + call gsinit + call _kmain + jp _exit + + ;; Ordering of segments for the linker. + .area _HOME + .area _CODE + .area _INITIALIZER + .area _GSINIT + .area _GSFINAL + + .area _DATA + .area _INITIALIZED + .area _BSEG + .area _BSS + .area _HEAP + + .area _CODE + +__clock:: + ld a,#2 + rst 0x08 + ret + +_exit:: + ;; Exit - special code to the emulator + ld a,#0 + rst 0x08 +1$: + halt + jr 1$ + + .area _GSINIT +gsinit:: + ; ld bc, #l__INITIALIZER + ld a, b + or a, c + jr Z, gsinit_next + ; ld de, #s__INITIALIZED + ; ld hl, #s__INITIALIZER + ldir +gsinit_next: - ;; call C main function - call _main + .area _GSFINAL + ret -.globl _main diff --git a/sw/z80/kernel/include/devices.h b/sw/z80/kernel/include/devices.h new file mode 100644 index 0000000..e8c183f --- /dev/null +++ b/sw/z80/kernel/include/devices.h @@ -0,0 +1,13 @@ +#ifndef __DEVICES_H__ +#define __DEVICES_H__ + +#define ADDR_DEV_ROM_L 0x0000 +#define ADDR_DEV_ROM_H 0x2000 + +#define ADDR_DEV_USART 0x4000 +#define ADDR_DEV_CTC 0x4100 +#define ADDR_DEV_PIO 0x4200 + +#define ADDR_DEV_RAM 0x8000 + +#endif diff --git a/sw/z80/kernel/include/pio.h b/sw/z80/kernel/include/pio.h new file mode 100644 index 0000000..5d289ca --- /dev/null +++ b/sw/z80/kernel/include/pio.h @@ -0,0 +1,35 @@ +#ifndef __PIO_H__ +#define __PIO_H__ + +#include "devices.h" +#include "types.h" + +#define PIO_A 0 +#define PIO_B 1 + +#define PIO_MODE_0 0 +#define PIO_MODE_1 1 +#define PIO_MODE_2 2 +#define PIO_MODE_3 3 + +#define PIO_INT_ACTIVE_HIGH (1<<5) +#define PIO_INT_AND_MODE (1<<6) +#define PIO_INT_ENABLE (1<<7) + + +void _pio_data(int port, uint8_t data); +void _pio_command(int port, uint8_t cmd); + +void pio_set_mode(int port, int mode); +void pio_set_interrupts(int port, int control); +void pio_set_interrupts_mask(int port, uint8_t mask); +void pio_set_io(int port, uint8_t io); + +// uint8_t pio_read_data(int port); + +inline int pio_read_pin(int port, uint8_t pin); +inline void pio_write_pin(int port, uint8_t pin); + +// TODO: implement mode (in/out/both) and interrupt vector + +#endif // __PIO_H__ diff --git a/sw/z80/kernel/include/types.h b/sw/z80/kernel/include/types.h index adde214..552b7e9 100644 --- a/sw/z80/kernel/include/types.h +++ b/sw/z80/kernel/include/types.h @@ -1,9 +1,13 @@ #ifndef __TYPES_H__ #define __TYPES_H__ +#define register_t volatile unsigned char + #define int8_t char #define uint8_t unsigned char #define int16_t int #define uint16_t unsigned int +#define size_t uint16_t + #endif diff --git a/sw/z80/kernel/include/usart.h b/sw/z80/kernel/include/usart.h new file mode 100644 index 0000000..3e5c070 --- /dev/null +++ b/sw/z80/kernel/include/usart.h @@ -0,0 +1,149 @@ +#ifndef __USART_H__ +#define __USART_H__ + +#include "types.h" +#include "devices.h" + +#include "string.h" + +// baudrate clock divisors +// values from TL16C550C datasheet (table 9 for 1.8432 MHz crystal) +#define USART_BAUDRATE_50 2304 +#define USART_BAUDRATE_75 1536 +#define USART_BAUDRATE_110 1047 +#define USART_BAUDRATE_134_5 857 +#define USART_BAUDRATE_150 768 +#define USART_BAUDRATE_300 384 +#define USART_BAUDRATE_600 192 +#define USART_BAUDRATE_1200 96 +#define USART_BAUDRATE_1800 64 +#define USART_BAUDRATE_2000 58 +#define USART_BAUDRATE_2400 48 +#define USART_BAUDRATE_3600 32 +#define USART_BAUDRATE_4800 24 +#define USART_BAUDRATE_7200 16 +#define USART_BAUDRATE_9600 12 +#define USART_BAUDRATE_19200 6 +#define USART_BAUDRATE_38400 3 +#define USART_BAUDRATE_56000 3 + +// parity +#define USART_PARITY_NONE 0 +#define USART_PARITY_EVEN 1 +#define USART_PARITY_ODD 2 + +// stop bits +#define USART_STOP_BITS_1 10 +#define USART_STOP_BITS_15 15 +#define USART_STOP_BITS_2 20 + +// word lenght +#define USART_WORD_LENGTH_5 0 +#define USART_WORD_LENGTH_6 1 +#define USART_WORD_LENGTH_7 2 +#define USART_WORD_LENGTH_8 3 + +// autoflow +#define USART_AUTOFLOW_ALL 3 +#define USART_AUTOFLOW_CTS 2 +#define USART_AUTOFLOW_OFF 0 + + +/* this structure is only for internal usage */ +struct _usart_device +{ + register_t buffer; // also used as LSB for divisor latch + + struct IER + { + volatile int received_data_interrupt :1; + volatile int transmitter_empty_interrupt :1; + volatile int receiver_line_status_interrupt :1; + volatile int modem_status_interrupt :1; + volatile int reserved :4; + } IER; + + struct IIR + { + volatile int interrupt_pending :1; + volatile int interrupt_id :3; + volatile int reserved :2; + volatile int fifos :2; + } IIR; + + struct FCR + { + volatile int fifo_enable :1; + volatile int receiver_fifo_rst :1; + volatile int trasmitter_fifo_rst :1; + volatile int dma_mode_select :1; + volatile int reserved :1; + volatile int receiver_trigger :2; + } FCR; + + struct LCR + { + volatile int word_length :2; + volatile int stop_bits :1; + volatile int parity :1; + volatile int even_parity :1; + volatile int stick_parity :1; + volatile int break_control :1; + volatile int divisor_latch_access :1; + } LCR; + + struct MCR + { + volatile int data_terminal_ready :1; + volatile int request_to_send :1; + volatile int out1; + volatile int out2; + volatile int loop; + volatile int autoflow :1; + volatile int reserved :2; + } MCR; + + struct LSR + { + volatile int data_ready :1; + volatile int overrun_error :1; + volatile int parity_error :1; + volatile int framing_error :1; + volatile int break_interrupt :1; + volatile int transmitter_holder_empty :1; + volatile int transmitter_empty :1; + volatile int fifo_recv_error :1; + } LSR; + + struct MSR + { + volatile int delta_cts :1; + volatile int delta_data_set_ready :1; + volatile int trailing_edge_ring_indicator :1; + volatile int delta_data_carrier_detect :1; + volatile int clear_to_send :1; + volatile int data_set_ready :1; + volatile int ring_indicator :1; + volatile int data_carrier_detect :1; + } MSR; + + register_t scratch; +}; + + +// setup functions (wrappers) +void usart_set_baudrate(uint16_t baudrate); +void usart_set_parity(int mode); +void usart_set_stop_bits(int count); +void usart_set_word_length(int length); +void usart_set_autoflow(int mode); + +inline void usart_init(uint16_t baudrate, int parity, int stop_bits); + +void usart_transmit(uint8_t data); +uint8_t usart_receive(); + +int usart_write(uint8_t *data, size_t size); +int usart_read(uint8_t *buffer, size_t count); + +#endif // __USART__H__ diff --git a/sw/z80/kernel/kernel.c b/sw/z80/kernel/kernel.c index fe87c3d..3d5aeb6 100644 --- a/sw/z80/kernel/kernel.c +++ b/sw/z80/kernel/kernel.c @@ -1,10 +1,7 @@ #include "types.h" +#include "usart.h" - -void main(void) +void kmain(void) { - int i, j = 20; - for (i = 0; i < 10; i++) { - j--; - } + usart_init(USART_BAUDRATE_9600, USART_PARITY_EVEN, USART_STOP_BITS_1); } diff --git a/sw/z80/kernel/pio.c b/sw/z80/kernel/pio.c new file mode 100644 index 0000000..4b9caee --- /dev/null +++ b/sw/z80/kernel/pio.c @@ -0,0 +1,18 @@ +#include "pio.h" + +static uint8_t *pio_port = (uint8_t *) ADDR_DEV_PIO; +static uint8_t *pio_ctrl = (uint8_t *) (ADDR_DEV_PIO + 2); + +void _pio_data(int port, uint8_t data) +{ + *(pio_port + port) = data; +} + +void _pio_command(int port, uint8_t cmd) +{ + *(pio_ctrl + port) = cmd; +} + +void pio_set_mode(int port, int mode) +{ +} diff --git a/sw/z80/kernel/usart.c b/sw/z80/kernel/usart.c new file mode 100644 index 0000000..9ec6dbd --- /dev/null +++ b/sw/z80/kernel/usart.c @@ -0,0 +1,91 @@ +#include "usart.h" + +static struct _usart_device *_usart = (struct _usart_device *) ADDR_DEV_USART; + +void usart_set_baudrate(uint16_t baudrate) +{ + // enable latch access + _usart->LCR.divisor_latch_access = 1; + _usart->buffer = 0x00FF & baudrate; // LSBs + memcpy(&_usart->IER, &(baudrate >>8), 1); + // _usart->IER = 0x00FF & (baudrate >> 8); // MSBs + _usart->LCR.divisor_latch_access = 0; +} + +void usart_set_parity(int mode) +{ + if (mode == USART_PARITY_EVEN) { + _usart->LCR.even_parity = 1; + } + else if (mode == USART_PARITY_ODD) { + _usart->LCR.even_parity = 0; + } + + _usart->LCR.parity = (mode == USART_PARITY_NONE) ? 0 : 1; +} + +void usart_set_stop_bits(int count) +{ + _usart->LCR.stop_bits = (count == USART_STOP_BITS_1) ? 0 : 1; +} + +void usart_word_length(int length) +{ + _usart->LCR.word_length = length; +} + +void usart_set_autoflow(int mode) +{ + _usart->MCR.autoflow = (mode == USART_AUTOFLOW_OFF) ? 0 : 1; + _usart->MCR.data_terminal_ready = (mode == USART_AUTOFLOW_ALL); +} + +inline void usart_init(uint16_t baudrate, int parity, int stop_bits) +{ + usart_set_baudrate(baudrate); + usart_set_parity(parity); + usart_set_stop_bits(stop_bits); + usart_set_autoflow(USART_AUTOFLOW_OFF); +} + +void usart_transmit(uint8_t data) +{ + _usart->buffer = data; + while (_usart->LSR.transmitter_holder_empty == 0); // wait +} + +uint8_t usart_receive() +{ + return _usart->buffer; +} + +int usart_write(uint8_t *data, size_t size) +{ + uint8_t *dp = data; + + while (size--) { + _usart->buffer = *(dp++); + while (_usart->LSR.transmitter_empty); + } + + // TODO: do something that actually counts for sent bytes + return size; +} + +int usart_read(uint8_t *buffer, size_t count) +{ + uint8_t *bp = buffer; + size_t read_count = 0; + + while (count--) { + *(bp++) = _usart->buffer; + // check for errors + if (_usart->LSR.framing_error || _usart->LSR.parity_error) { + bp--; // delete last byte (?) + } else { + read_count++; + } + } + + return read_count; +} diff --git a/sw/z80/libc/include/stdio.h b/sw/z80/libc/include/stdio.h new file mode 100644 index 0000000..b31cdfd --- /dev/null +++ b/sw/z80/libc/include/stdio.h @@ -0,0 +1,11 @@ +#ifndef __STDIO_H__ +#define __STDIO_H__ + +#include "types.h" + +extern uint8_t *stdout, stderr; + +void putc(char ch, uint8_t *buffer); +int printf(const char *fmt, ...); + +#endif diff --git a/sw/z80/libc/include/string.h b/sw/z80/libc/include/string.h new file mode 100644 index 0000000..f224c87 --- /dev/null +++ b/sw/z80/libc/include/string.h @@ -0,0 +1,8 @@ +#ifndef __STRING_H__ +#define __STRING_H__ + +#include "types.h" + +void *memcpy(void *dest, const void *src, size_t n); + +#endif diff --git a/sw/z80/libc/include/sysio.h b/sw/z80/libc/include/sysio.h new file mode 100644 index 0000000..5d1f5ae --- /dev/null +++ b/sw/z80/libc/include/sysio.h @@ -0,0 +1,55 @@ +#ifndef __SYSIO_H__ +#define __SYSIO_H__ + +#include "types.h" + +/* +* Memory management +*/ + +void * malloc(uint16_t size); +uint16_t malloc_size(void * address); +void free(void * address); + +/* +* File management +*/ + +#define F_WRITE "w" +#define F_READ "r" +#define F_BIN_WRITE "wb" +#define F_BIN_READ "rb" + +#define F_READ_CODE 0x0 +#define F_WRITE_CODE 0x1 +#define F_BIN_READ_CODE 0x2 +#define F_BIN_WRITE_CODE 0x3 + +#define F_PERM_READ 0x0 +#define F_PERM_WRITE 0x1 +#define F_PERM_RW 0x2 + +struct file { + + const char * path; + unsigned int mode:4; + unsigned int permission:4; +}; + +#define FILE struct file + +FILE * fopen(const char * path, const char * mode); +uint8_t fclose(FILE * file); + +// TODO: other functions + +/* +* Processes management +*/ + +#define PID uint16_t + +void exit(); // exit this program +void interrupt(PID) + +#endif
\ No newline at end of file diff --git a/sw/z80/libc/stdio.c b/sw/z80/libc/stdio.c new file mode 100644 index 0000000..c2548d6 --- /dev/null +++ b/sw/z80/libc/stdio.c @@ -0,0 +1,12 @@ +#include "stdio.h" + +void putc(char ch, uint8_t *buffer) +{ + *buffer = ch; + *(++buffer) = '\0'; +} + + +int printf(const char *fmt, ...) +{ +} diff --git a/sw/z80/libc/string.c b/sw/z80/libc/string.c new file mode 100644 index 0000000..fd6a7ff --- /dev/null +++ b/sw/z80/libc/string.c @@ -0,0 +1,13 @@ +#include "string.h" + +void *memcpy(void *dest, void *src, size_t n) +{ + char *dp = dest; + char *sp = src; + + while (n--) { + *dp++ = *sp++; + } + + return dest; +} diff --git a/sw/z80/makefile b/sw/z80/makefile index ecdd9a4..3d682ca 100644 --- a/sw/z80/makefile +++ b/sw/z80/makefile @@ -4,6 +4,7 @@ OSNAME := helvetiOS CSOURCES := $(wildcard kernel/*.c) $(wildcard libc/*.c) +OBJECTS := $(patsubst %.c,build/%.rel,$(CSOURCES)) HEXFILE := build/$(OSNAME).hex BINARY := build/$(OSNAME).bin @@ -12,26 +13,33 @@ BINARY := build/$(OSNAME).bin CC := sdcc -CFLAGS := -mz80 --no-std-crt0 crt0.rel \ +CFLAGS := -mz80 \ -I kernel/include -I libc/include -DDEBUG -LDFLAGS := --code-loc 0x0800 --data-loc 0x8000 +LDFLAGS := -mz80 --no-std-crt0 crt0.rel \ + --code-loc 0x0800 --data-loc 0x8000 +.PHONY: dirs dis clean all: $(BINARY) # build binary -$(BINARY): $(CSOURCES) crt0.rel - mkdir -p build - $(CC) $(CFLAGS) $(LDFLSGS) $(CSOURCES) -o $(HEXFILE) +$(BINARY): $(OBJECTS) dirs + $(CC) $(LDFLAGS) $(OBJECTS) -o $(HEXFILE) xxd -r -p $(HEXFILE) $(BINARY) +$(OBJECTS): build/%.rel : %.c $(CSOURCES) dirs crt0.rel + $(CC) $(CFLAGS) -c $< -o $@ + crt0.rel: crt0.s sdasz80 -o $< +dirs: + mkdir -p build build/kernel build/libc + dis: $(BINARY) z80dasm -a -g 0h $< -o $(OSNAME).s clean: - - rm build/* + - rm -rd build/* - rm $(OSNAME).s - rm crt0.rel |
