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authorNao Pross <naopross@thearcway.org>2017-04-13 16:03:11 +0200
committerNao Pross <naopross@thearcway.org>2017-04-13 16:03:11 +0200
commit985e16b181fd55e28538f2d4524550bd425b86e9 (patch)
tree3d444d9e6a651a4345069c8fc96a60a811a57ac8 /doc/datasheets
parentMerge branch 'master' into naopross (diff)
downloadz80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.tar.gz
z80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.zip
switch from GAL (pld) to M4 32/32 CPLD
add M4 32/32 CPLD datasheet new VHDL code with better control over the address space thanks to the M4 which has a 16 bit input port
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diff --git a/doc/datasheets/M4-32_32-15JC.pdf b/doc/datasheets/M4-32_32-15JC.pdf
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