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authorNao Pross <naopross@thearcway.org>2017-05-18 14:44:25 +0200
committerNao Pross <naopross@thearcway.org>2017-05-18 14:44:25 +0200
commit8992f39ebcbf82fd02b246dcf8f8ed3a69f7b81b (patch)
tree598dcf9be6ab043fdf68649b588fd5a51bfc6c00 /hw/History/MainBoard.~(177).PcbDoc.Zip
parentwires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550 (diff)
downloadz80uPC-8992f39ebcbf82fd02b246dcf8f8ed3a69f7b81b.tar.gz
z80uPC-8992f39ebcbf82fd02b246dcf8f8ed3a69f7b81b.zip
wiring for P4 and P5 (I/O ports) and circuits for CLKs and RST
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