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authorNao Pross <naopross@thearcway.org>2017-05-09 11:21:42 +0200
committerNao Pross <naopross@thearcway.org>2017-05-09 11:21:42 +0200
commit7439592a67e7f63a286dc6527164834329fdc29b (patch)
tree695b535f42b75cf8af32934b5d07af293a352a77 /hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG
parentcomplete wiring for serial interface connector and logic (diff)
downloadz80uPC-7439592a67e7f63a286dc6527164834329fdc29b.tar.gz
z80uPC-7439592a67e7f63a286dc6527164834329fdc29b.zip
created new layout (starting over)
the old layout is still under hw/MainBoard1.PcbDoc
Diffstat (limited to 'hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG')
-rw-r--r--hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG21
1 files changed, 21 insertions, 0 deletions
diff --git a/hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG b/hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG
new file mode 100644
index 0000000..fb7a000
--- /dev/null
+++ b/hw/Project Logs for z80uPC/MainBoard PCB ECO 08.05.2017 09-42-04.LOG
@@ -0,0 +1,21 @@
+Removed Pin From Net: NetName=A12 Pin=U4-18
+Removed Pin From Net: NetName=A13 Pin=U4-19
+Removed Pin From Net: NetName=A14 Pin=U4-20
+Removed Pin From Net: NetName=A15 Pin=U4-21
+Added Pin To Net: NetName=A15 Pin=U4-36
+Added Pin To Net: NetName=A14 Pin=U4-37
+Added Pin To Net: NetName=A13 Pin=U4-38
+Added Pin To Net: NetName=A12 Pin=U4-39
+Added Pin To Net: NetName=D3 Pin=U4-40
+Added Pin To Net: NetName=D2 Pin=U4-41
+Added Pin To Net: NetName=D1 Pin=U4-42
+Added Pin To Net: NetName=D0 Pin=U4-43
+Added Pin To Net: NetName=MMU_A12 Pin=U4-18
+Added Net: Name=MMU_A12
+Added Pin To Net: NetName=MMU_A13 Pin=U4-19
+Added Net: Name=MMU_A13
+Added Pin To Net: NetName=MMU_A14 Pin=U4-20
+Added Net: Name=MMU_A14
+Added Pin To Net: NetName=MMU_A15 Pin=U4-21
+Added Net: Name=MMU_A15
+Added Member To Class: ClassName=IODevices Member=Component P2 Header 8X2