diff options
| author | Nao Pross <naopross@thearcway.org> | 2017-04-13 16:03:11 +0200 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-04-13 16:03:11 +0200 |
| commit | 985e16b181fd55e28538f2d4524550bd425b86e9 (patch) | |
| tree | 3d444d9e6a651a4345069c8fc96a60a811a57ac8 /sw/cpld/ADDRESS_DECODER.syn | |
| parent | Merge branch 'master' into naopross (diff) | |
| download | z80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.tar.gz z80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.zip | |
switch from GAL (pld) to M4 32/32 CPLD
add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port
Diffstat (limited to 'sw/cpld/ADDRESS_DECODER.syn')
| -rw-r--r-- | sw/cpld/ADDRESS_DECODER.syn | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sw/cpld/ADDRESS_DECODER.syn b/sw/cpld/ADDRESS_DECODER.syn new file mode 100644 index 0000000..419b6ba --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.syn @@ -0,0 +1,11 @@ +JDF B +// Created by Version 2.0 +PROJECT ADDRESS_DECODER +DESIGN address_decoder Normal +DEVKIT M4A3-32/32-10JC +ENTRY Pure VHDL +MODULE address_decoder.vhd +MODSTYLE ADDRESS_DECODER Normal +SYNTHESIS_TOOL Synplify +SIMULATOR_TOOL ActiveHDL +TOPMODULE ADDRESS_DECODER |