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authorNao Pross <naopross@thearcway.org>2017-11-23 14:34:55 +0100
committerNao Pross <naopross@thearcway.org>2017-11-23 14:34:55 +0100
commit141137dfe5bdc7400d5cc1ad388b670f9f2e9446 (patch)
treebef58de3c44787dadb22ec9cf452a3606ddd6708 /sw/cpld/address_decoder.log
parentImprovements in PIO driver, pio test rewritten in inline asm (diff)
downloadz80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.tar.gz
z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.zip
update cpld files from VHDL dev machine and delete programmer code (unused)
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1 files changed, 46 insertions, 0 deletions
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+|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+
+*** Source file is address_decoder.tt4 . Device is M4-32/32-15JC .
+
+<Note> F35109: For this device, all input pairing is ignored since input
+ registers or latches do not exist. All signals must pass
+ through the central switch matrix before being latched or
+ registered.
+<Note> F40016: 0 pins have been reserved out of 34 .
+<Note> F40021: 34 pins are available after reservation, 21 are required
+ by the design.
+<Note> F35065: For outputs, implicit output enables will be set to VCC.
+
+*** End of Pla2db.
+Check preplaced pins/nodes
+Check preplaced blocks
+Check unreferenced pins/nodes
+Check clock rules
+
+List of non-global clocks:
+ None.
+
+*** End of Normalization.
+
+*** End of DRC.
+
+*** Start Partitioning
+
+*** Partitioning successful.
+
+
+*** Starting Place&Route
+
+*** Place&Route Successful
+*** The JEDEC file generated is address_decoder.jed .
+*** Report Generator invoked.
+*** Report Generator end.
+
+// Fitting successful.
+// ERROR count 0 WARNING count 0 .