diff options
| author | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
| commit | 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 (patch) | |
| tree | bef58de3c44787dadb22ec9cf452a3606ddd6708 /sw/cpld/address_decoder.sdf | |
| parent | Improvements in PIO driver, pio test rewritten in inline asm (diff) | |
| download | z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.tar.gz z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.zip | |
update cpld files from VHDL dev machine and delete programmer code (unused)
Diffstat (limited to 'sw/cpld/address_decoder.sdf')
| -rwxr-xr-x | sw/cpld/address_decoder.sdf | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/sw/cpld/address_decoder.sdf b/sw/cpld/address_decoder.sdf new file mode 100755 index 0000000..3823d8f --- /dev/null +++ b/sw/cpld/address_decoder.sdf @@ -0,0 +1,204 @@ +// SDF delay-file
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "address_decoder")
+ (DATE "11/13/2017 11:47:12")
+ (VENDOR "Lattice Semiconductor")
+ (PROGRAM "SDF Generator")
+ (VERSION "8.3.02.12_DE_HDL_BASE Data sheet version: 1.01")
+ (DIVIDER /)
+ (VOLTAGE :5.0:)
+ (PROCESS "typical")
+ (TEMPERATURE :25:)
+ (TIMESCALE 100ps)
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_15_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSROML_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSROMH_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSRAM_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSUART_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSCTC_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSPIO_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_14_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_13_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_12_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_15_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSRAM_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_14_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_13_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_12_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSROML_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSROMH_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSUART_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSCTC_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSPIO_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+)
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