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| author | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-11-23 14:34:55 +0100 |
| commit | 141137dfe5bdc7400d5cc1ad388b670f9f2e9446 (patch) | |
| tree | bef58de3c44787dadb22ec9cf452a3606ddd6708 /sw/cpld/address_decoder.trp | |
| parent | Improvements in PIO driver, pio test rewritten in inline asm (diff) | |
| download | z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.tar.gz z80uPC-141137dfe5bdc7400d5cc1ad388b670f9f2e9446.zip | |
update cpld files from VHDL dev machine and delete programmer code (unused)
Diffstat (limited to 'sw/cpld/address_decoder.trp')
| -rwxr-xr-x | sw/cpld/address_decoder.trp | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/sw/cpld/address_decoder.trp b/sw/cpld/address_decoder.trp new file mode 100755 index 0000000..2c329e3 --- /dev/null +++ b/sw/cpld/address_decoder.trp @@ -0,0 +1,75 @@ +
+Timing Report for STAMP
+
+// Project = address_decoder
+// Family = M4
+// Device = M4-32/32
+// Speed = -15
+// Voltage = 5.0
+// Operating Condition = COM
+// Data sheet version = 1.01
+
+// Pass Bidirection = OFF
+// Pass S/R = OFF
+// Pass Latch = OFF
+// Pass Clock = OFF
+// Maximum Paths = 20
+// T_SU Endpoints D/T inputs = ON
+// T_SU Endpoints CE inputs = OFF
+// T_SU Endpoints S/R inputs = OFF
+
+
+Section IO
+ //DESTINATION NODES;
+ CSCTC [out]
+ CSPIO [out]
+ CSRAM [out]
+ CSROMH [out]
+ CSROML [out]
+ CSUART [out]
+ MMU_OUT[12] [out]
+ MMU_OUT[13] [out]
+ MMU_OUT[14] [out]
+ MMU_OUT[15] [out]
+
+ //SOURCE NODES;
+ MMU_IN[2] [in]
+ MMU_IN[3] [in]
+ MMU_IN[4] [in]
+ MMU_IN[5] [in]
+ MMU_IN[6] [in]
+ MMU_IN[7] [in]
+ MMU_IN[8] [in]
+ MMU_IN[9] [in]
+ MMU_IN[10] [in]
+ MMU_IN[11] [in]
+ MMU_IN[12] [in]
+ MMU_IN[13] [in]
+ MMU_IN[14] [in]
+ MMU_IN[15] [in]
+
+
+Section tPD
+
+ Delay Location(From => To) Source Destination
+ ===== ==================== ====== ===========
+ 15.0 p7 => p27 MMU_IN[2] CSUART
+ 15.0 p6 => p27 MMU_IN[3] CSUART
+ 15.0 p5 => p27 MMU_IN[4] CSUART
+ 15.0 p4 => p27 MMU_IN[5] CSUART
+ 15.0 p3 => p27 MMU_IN[6] CSUART
+ 15.0 p2 => p27 MMU_IN[7] CSUART
+ 15.0 p14 => p28 MMU_IN[8] CSCTC
+ 15.0 p14 => p29 MMU_IN[8] CSPIO
+ 15.0 p14 => p27 MMU_IN[8] CSUART
+ 15.0 p15 => p28 MMU_IN[9] CSCTC
+ 15.0 p15 => p29 MMU_IN[9] CSPIO
+ 15.0 p15 => p27 MMU_IN[9] CSUART
+ 15.0 p16 => p28 MMU_IN[10] CSCTC
+ 15.0 p16 => p29 MMU_IN[10] CSPIO
+ 15.0 p16 => p27 MMU_IN[10] CSUART
+ 15.0 p17 => p28 MMU_IN[11] CSCTC
+ 15.0 p17 => p29 MMU_IN[11] CSPIO
+ 15.0 p17 => p27 MMU_IN[11] CSUART
+ 15.0 p18 => p28 MMU_IN[12] CSCTC
+ 15.0 p18 => p29 MMU_IN[12] CSPIO
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