switch from GAL (pld) to M4 32/32 CPLD

add M4 32/32 CPLD datasheet
new VHDL code with better control over the address space thanks to the
M4 which has a 16 bit input port

13 files changed, 621 insertions, 0 deletions

diff --git a/sw/cpld/ADDRESS_DECODER.STY b/sw/cpld/ADDRESS_DECODER.STY
new file mode 100644
index 0000000..afd24c5
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.STY
@@ -0,0 +1,4 @@
+[STRATEGY-LIST]
+Normal=True, 1491209776
+[synthesis-type]
+tool=Synplify
diff --git a/sw/cpld/ADDRESS_DECODER.lci b/sw/cpld/ADDRESS_DECODER.lci
new file mode 100644
index 0000000..47875d5
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.lci
@@ -0,0 +1,107 @@
+
+[Device]
+Family = M4A3;
+PartNumber = M4A3-32/32-10JC;
+Package = 44PLCC;
+PartType = M4A3-32/32;
+Speed = -10;
+Operating_condition = COM;
+Status = Production;
+
+[Revision]
+Parent = m4a332.lci;
+DATE = 2002;
+TIME = 0:00:00;
+Source_Format = Pure_VHDL;
+Synthesis = Synplify;
+
+[Ignore Assignments]
+
+[Clear Assignments]
+
+[Backannotate Assignments]
+
+[Global Constraints]
+
+[Location Assignments]
+layer = OFF;
+
+[Group Assignments]
+layer = OFF;
+
+[Resource Reservations]
+layer = OFF;
+
+[Fitter Report Format]
+
+[Power]
+
+[Source Constraint Option]
+
+[Fast Bypass]
+
+[OSM Bypass]
+
+[Input Registers]
+
+[Netlist/Delay Format]
+NetList = VHDL;
+
+[IO Types]
+layer = OFF;
+
+[Pullup]
+
+[Slewrate]
+
+[Region]
+
+[Timing Constraints]
+
+[HSI Attributes]
+
+[Input Delay]
+
+[opt global constraints list]
+
+[Explorer User Settings]
+
+[Pin attributes list]
+
+[global constraints list]
+
+[Global Constraints Process Update]
+
+[pin lock limitation]
+
+[LOCATION ASSIGNMENTS LIST]
+
+[RESOURCE RESERVATIONS LIST]
+
+[individual constraints list]
+
+[Attributes list setting]
+
+[Timing Analyzer]
+
+[PLL Assignments]
+
+[Dual Function Macrocell]
+
+[Explorer Results]
+
+[VHDL synplify constraints]
+
+[VHDL spectrum constraints]
+
+[verilog synplify constraints]
+
+[verilog spectrum constraints]
+
+[VHDL synplify constraints list]
+
+[VHDL spectrum constraints list]
+
+[verilog synplify constraints list]
+
+[verilog spectrum constraints list]
diff --git a/sw/cpld/ADDRESS_DECODER.lct b/sw/cpld/ADDRESS_DECODER.lct
new file mode 100644
index 0000000..47875d5
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.lct
@@ -0,0 +1,107 @@
+
+[Device]
+Family = M4A3;
+PartNumber = M4A3-32/32-10JC;
+Package = 44PLCC;
+PartType = M4A3-32/32;
+Speed = -10;
+Operating_condition = COM;
+Status = Production;
+
+[Revision]
+Parent = m4a332.lci;
+DATE = 2002;
+TIME = 0:00:00;
+Source_Format = Pure_VHDL;
+Synthesis = Synplify;
+
+[Ignore Assignments]
+
+[Clear Assignments]
+
+[Backannotate Assignments]
+
+[Global Constraints]
+
+[Location Assignments]
+layer = OFF;
+
+[Group Assignments]
+layer = OFF;
+
+[Resource Reservations]
+layer = OFF;
+
+[Fitter Report Format]
+
+[Power]
+
+[Source Constraint Option]
+
+[Fast Bypass]
+
+[OSM Bypass]
+
+[Input Registers]
+
+[Netlist/Delay Format]
+NetList = VHDL;
+
+[IO Types]
+layer = OFF;
+
+[Pullup]
+
+[Slewrate]
+
+[Region]
+
+[Timing Constraints]
+
+[HSI Attributes]
+
+[Input Delay]
+
+[opt global constraints list]
+
+[Explorer User Settings]
+
+[Pin attributes list]
+
+[global constraints list]
+
+[Global Constraints Process Update]
+
+[pin lock limitation]
+
+[LOCATION ASSIGNMENTS LIST]
+
+[RESOURCE RESERVATIONS LIST]
+
+[individual constraints list]
+
+[Attributes list setting]
+
+[Timing Analyzer]
+
+[PLL Assignments]
+
+[Dual Function Macrocell]
+
+[Explorer Results]
+
+[VHDL synplify constraints]
+
+[VHDL spectrum constraints]
+
+[verilog synplify constraints]
+
+[verilog spectrum constraints]
+
+[VHDL synplify constraints list]
+
+[VHDL spectrum constraints list]
+
+[verilog synplify constraints list]
+
+[verilog spectrum constraints list]
diff --git a/sw/cpld/ADDRESS_DECODER.naf b/sw/cpld/ADDRESS_DECODER.naf
new file mode 100644
index 0000000..fe52855
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.naf
@@ -0,0 +1,22 @@
+PA[15]  i
+PA[14]  i
+PA[13]  i
+PA[12]  i
+PA[11]  i
+PA[10]  i
+PA[9]  i
+PA[8]  i
+PA[7]  i
+PA[6]  i
+PA[5]  i
+PA[4]  i
+PA[3]  i
+PA[2]  i
+PA[1]  i
+PA[0]  i
+CSROMH  o
+CSROML  o
+CSRAM  o
+CSUART  o
+CSCTC  o
+CSPIO  o
diff --git a/sw/cpld/ADDRESS_DECODER.syn b/sw/cpld/ADDRESS_DECODER.syn
new file mode 100644
index 0000000..419b6ba
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.syn
@@ -0,0 +1,11 @@
+JDF B
+// Created by Version 2.0 
+PROJECT ADDRESS_DECODER
+DESIGN address_decoder Normal
+DEVKIT M4A3-32/32-10JC
+ENTRY Pure VHDL
+MODULE address_decoder.vhd
+MODSTYLE ADDRESS_DECODER Normal
+SYNTHESIS_TOOL Synplify
+SIMULATOR_TOOL ActiveHDL
+TOPMODULE ADDRESS_DECODER
diff --git a/sw/cpld/ADDRESS_DECODER.tcl b/sw/cpld/ADDRESS_DECODER.tcl
new file mode 100644
index 0000000..4c9fe3f
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER.tcl
@@ -0,0 +1,270 @@
+
+########## Tcl recorder starts at 04/03/17 14:05:56 ##########
+
+set version "2.0"
+set proj_dir "//nas001/account_PIF/_prossn/SAMB_3/lab3/projects/z80uPC/sw/cpld"
+cd $proj_dir
+
+# Get directory paths
+set pver $version
+regsub -all {\.} $pver {_} pver
+set lscfile "lsc_"
+append lscfile $pver ".ini"
+set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
+set lsvini_path [file join $lsvini_dir $lscfile]
+if {[catch {set fid [open $lsvini_path]} msg]} {
+	 puts "File Open Error: $lsvini_path"
+	 return false
+} else {set data [read $fid]; close $fid }
+foreach line [split $data '\n'] { 
+	set lline [string tolower $line]
+	set lline [string trim $lline]
+	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
+	if {$path && [regexp {^\[} $lline]} {set path 0; break}
+	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
+	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
+	if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}
+
+set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
+regsub -all "\"" $cpld_bin "" cpld_bin
+set cpld_bin [file join $cpld_bin]
+set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
+regsub -all "\"" $install_dir "" install_dir
+set install_dir [file join $install_dir]
+set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
+regsub -all "\"" $fpga_dir "" fpga_dir
+set fpga_dir [file join $fpga_dir]
+set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
+regsub -all "\"" $fpga_bin "" fpga_bin
+set fpga_bin [file join $fpga_bin]
+
+if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
+   set env(PATH) "$fpga_bin;$env(PATH)" }
+
+if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
+   set env(PATH) "$cpld_bin;$env(PATH)" }
+
+lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
+package require runcmd
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:05:56 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:07:59 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:07:59 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:08:48 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:08:48 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:11:44 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:11:44 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:22:22 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:22:22 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:22:30 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:22:31 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:28:11 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:28:11 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:56:18 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:56:18 ###########
+
+
+########## Tcl recorder starts at 04/03/17 14:56:23 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/03/17 14:56:23 ###########
+
+
+########## Tcl recorder starts at 04/13/17 10:29:16 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/13/17 10:29:16 ###########
+
+
+########## Tcl recorder starts at 04/13/17 10:29:50 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/13/17 10:29:50 ###########
+
+
+########## Tcl recorder starts at 04/13/17 10:33:10 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/13/17 10:33:10 ###########
+
+
+########## Tcl recorder starts at 04/13/17 10:33:11 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/13/17 10:33:11 ###########
+
+
+########## Tcl recorder starts at 04/13/17 10:34:43 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 04/13/17 10:34:43 ###########
+
diff --git a/sw/cpld/ADDRESS_DECODER_tcl.ini b/sw/cpld/ADDRESS_DECODER_tcl.ini
new file mode 100644
index 0000000..fae7b5f
--- /dev/null
+++ b/sw/cpld/ADDRESS_DECODER_tcl.ini
@@ -0,0 +1,5 @@
+[Tcl]
+Start = Yes;
+Process = YES;
+Append = YES;
+TclFilename = ADDRESS_DECODER.tcl;
diff --git a/sw/cpld/address_decoder.jhd b/sw/cpld/address_decoder.jhd
new file mode 100644
index 0000000..19ef983
--- /dev/null
+++ b/sw/cpld/address_decoder.jhd
@@ -0,0 +1,3 @@
+
+
+MODULE ADDRESS_DECODER
diff --git a/sw/cpld/address_decoder.jid b/sw/cpld/address_decoder.jid
new file mode 100644
index 0000000..f0d5286
--- /dev/null
+++ b/sw/cpld/address_decoder.jid
@@ -0,0 +1 @@
+. ADDRESS_DECODER address_decoder.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld\address_decoder.vhd
diff --git a/sw/cpld/address_decoder.rev b/sw/cpld/address_decoder.rev
new file mode 100644
index 0000000..e8bfb3d
--- /dev/null
+++ b/sw/cpld/address_decoder.rev
@@ -0,0 +1,3 @@
+<SYNPROJ_Revision_Control>
+<RevisionControl_Info/>
+</SYNPROJ_Revision_Control>
diff --git a/sw/cpld/address_decoder.vhd b/sw/cpld/address_decoder.vhd
new file mode 100644
index 0000000..2c80f86
--- /dev/null
+++ b/sw/cpld/address_decoder.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity ADDRESS_DECODER is
+
+port(
+	-- address input
+	PA: in unsigned(15 downto 0);
+
+	-- chip selects output
+	-- memory
+	CSROMH: out std_logic;
+	CSROML: out std_logic;
+	CSRAM : out std_logic;
+	-- io chips
+	CSUART: out std_logic;
+	CSCTC : out std_logic;
+	CSPIO : out std_logic
+);
+
+end;
+
+architecture Behavioral of ADDRESS_DECODER is
+begin
+	-- memory
+	CSROMH <= 0 when ((PA >= x"0000") and (PA < x"2000"));
+	CSROML <= 0 when ((PA >= x"4000") and (PA < x"4000"));
+	CSRAM  <= 0 when (PA >= x"D000");
+	-- io chips
+	CSUART <= 0 when ((PA >= x"4000") and (PA < x"4008"));
+	-- CSCTC
+	-- CSPIO 
+
+end Behavioral;
+
diff --git a/sw/cpld/automake.log b/sw/cpld/automake.log
new file mode 100644
index 0000000..f24e14f
--- /dev/null
+++ b/sw/cpld/automake.log
@@ -0,0 +1,10 @@
+ispLEVER Auto-Make Log File
+---------------------------
+
+Updating: Hierarchy
+Start to record tcl script...
+Finished recording TCL script.
+
+Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\vhd2jhd.exe address_decoder.vhd -o address_decoder.jhd -m "C:\ispLEVER_Classic2\ispcpld/generic/lib/vhd/location.map" -p "C:\ispLEVER_Classic2\ispcpld/generic/lib"'
+
+Done: completed successfully.
diff --git a/sw/cpld/syndos.env b/sw/cpld/syndos.env
new file mode 100644
index 0000000..16036da
--- /dev/null
+++ b/sw/cpld/syndos.env
@@ -0,0 +1,41 @@
+ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5
+DIOEDA_ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5
+DIOEDA_ActiveHDL=C:\ispLEVER_Classic2\active-hdl\BIN
+DIOEDA_ActiveHDLPath=C:\ispLEVER_Classic2\active-hdl\BIN
+DIOEDA_AppNotes=C:\ispLEVER_Classic2\ispcpld\bin
+DIOEDA_Bin=C:\ispLEVER_Classic2\ispcpld\bin
+DIOEDA_Config=C:\ispLEVER_Classic2\ispcpld\config
+DIOEDA_CONTEXT=ispLEVER CLASSIC
+DIOEDA_DSPPATH=C:\ispLEVER_Classic2\ispLeverDSP
+DIOEDA_EPICPATH=C:\ispLEVER_Classic2\ispfpga\bin\nt
+DIOEDA_Examples=C:\ispLEVER_Classic2\examples
+DIOEDA_FPGABinPath=C:\ispLEVER_Classic2\ispfpga\bin\nt
+DIOEDA_FPGAPath=C:\ispLEVER_Classic2\ispfpga
+DIOEDA_HDLExplorer=C:\ispLEVER_Classic2\hdle\win32
+DIOEDA_INI=C:\lsc_env
+DIOEDA_ispVM=C:\ispLEVER_Classic2\ispvmsystem
+DIOEDA_ispVMSystem=C:\ispLEVER_Classic2\ispvmsystem
+DIOEDA_License=C:\ispLEVER_Classic2\license
+DIOEDA_LSEPath=C:\ispLEVER_Classic2\lse
+DIOEDA_MachPath=C:\ispLEVER_Classic2\ispcpld\bin
+DIOEDA_Manuals=C:\ispLEVER_Classic2\ispcpld\manuals
+DIOEDA_ModelSim=C:\ispLEVER_Classic2\modelsim\win32loem
+DIOEDA_ModelsimPath=C:\ispLEVER_Classic2\modelsim\win32loem
+DIOEDA_PDSPath=C:\ispLEVER_Classic2\ispcomp
+DIOEDA_Precision=C:\isptools\precision
+DIOEDA_PrecisionPath=C:\isptools\precision
+DIOEDA_ProductName=ispLEVER
+DIOEDA_ProductPrefix=SYN
+DIOEDA_ProductTitle=ispLEVER
+DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N
+DIOEDA_ProductVersion=2.0.00.17
+DIOEDA_ProgramFolder=ispLEVER Classic 2.0
+DIOEDA_Root=C:\ispLEVER_Classic2\ispcpld
+DIOEDA_Spectrum=C:\isptools\spectrum
+DIOEDA_SpectrumPath=C:\isptools\spectrum
+DIOEDA_Synplify=C:\ispLEVER_Classic2\synpbase
+DIOEDA_SynplifyPath=C:\ispLEVER_Classic2\synpbase
+DIOEDA_Synthesis=C:\ispLEVER_Classic2\lse\bin\nt
+DIOEDA_Tutorial=C:\ispLEVER_Classic2\ispcpld\tutorial
+DIOPRODUCT=ispLEVER
+PATH=C:\ispLEVER_Classic2\ispcpld\bin