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authorNao Pross <naopross@thearcway.org>2017-04-13 16:03:11 +0200
committerNao Pross <naopross@thearcway.org>2017-04-13 16:03:11 +0200
commit985e16b181fd55e28538f2d4524550bd425b86e9 (patch)
tree3d444d9e6a651a4345069c8fc96a60a811a57ac8 /sw/pld/ADDRESS_DECODER.jed
parentMerge branch 'master' into naopross (diff)
downloadz80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.tar.gz
z80uPC-985e16b181fd55e28538f2d4524550bd425b86e9.zip
switch from GAL (pld) to M4 32/32 CPLD
add M4 32/32 CPLD datasheet new VHDL code with better control over the address space thanks to the M4 which has a 16 bit input port
Diffstat (limited to 'sw/pld/ADDRESS_DECODER.jed')
-rw-r--r--sw/pld/ADDRESS_DECODER.jed28
1 files changed, 0 insertions, 28 deletions
diff --git a/sw/pld/ADDRESS_DECODER.jed b/sw/pld/ADDRESS_DECODER.jed
deleted file mode 100644
index 0525a9d..0000000
--- a/sw/pld/ADDRESS_DECODER.jed
+++ /dev/null
@@ -1,28 +0,0 @@
-
-CUPL(WM) 5.0a Serial# 60008009
-Device g16v8as Library DLIB-h-40-2
-Created Fri Mar 17 15:18:30 2017
-Name ADDRESS_DECODER
-Partno 00
-Revision 01
-Date 17.03.2017
-Designer Engineer
-Company SAM Bellinzona
-Assembly None
-Location
-*QP20
-*QF2194
-*G0
-*F0
-*L00512 01110111101110111011011110111011
-*L00768 10110111101110111011011110111011
-*L01024 10111011101110111011011110111011
-*L01280 11111111111111111111111111111011
-*L01536 11111111111111111111011110111011
-*L01792 11111111111111111111101110111011
-*L02048 00000100001100000011000000100000
-*L02112 00000000110000001111111111111111
-*L02144 11111111111111111111111111111111
-*L02176 111111111111111110
-*C1E45
-*A086 \ No newline at end of file