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| author | Nao Pross <naopross@thearcway.org> | 2017-11-09 13:17:35 +0100 |
|---|---|---|
| committer | Nao Pross <naopross@thearcway.org> | 2017-11-09 13:17:35 +0100 |
| commit | 3b2f2ea6c6fbfcb23ea9ab324c83d602d45a8820 (patch) | |
| tree | 2362bfb36432e551f2f0025d4f12554bddc863c9 /sw/z80/drivers/include/pio.h | |
| parent | Update gitignore and add sdcc manual (diff) | |
| download | z80uPC-3b2f2ea6c6fbfcb23ea9ab324c83d602d45a8820.tar.gz z80uPC-3b2f2ea6c6fbfcb23ea9ab324c83d602d45a8820.zip | |
Update makefile, and bug fix in pio driver and usart
Diffstat (limited to '')
| -rw-r--r-- | sw/z80/drivers/include/pio.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/sw/z80/drivers/include/pio.h b/sw/z80/drivers/include/pio.h index a4b6fc2..a1137e4 100644 --- a/sw/z80/drivers/include/pio.h +++ b/sw/z80/drivers/include/pio.h @@ -10,23 +10,24 @@ // registers #define PIO_REG_DATA 0 -#define PIO_REG_CTRL 1 +#define PIO_REG_CTRL 2 // #define PIO_REG_DATA_A (PIO_A + PIO_REG_PORT) // #define PIO_REG_DATA_B 1 (PIO_B + PIO_REG_PORT) // #define PIO_REG_CTRL_A 2 (PIO_A + PIO_REG_CTRL) // #define PIO_REG_CTRL_B 3 (PIO_B + PIO_REG_CTRL) -#define PIO_MODE_BYTE_IN 0 -#define PIO_MODE_BYTE_OUT 1 -#define PIO_MODE_BYTE_BI 2 -#define PIO_MODE_BIT_IO 3 +#define PIO_MODE_BYTE_OUT 0 // mode 0 +#define PIO_MODE_BYTE_IN 1 // mode 1 +#define PIO_MODE_BYTE_BI 2 // mode 2 +#define PIO_MODE_BIT_IO 3 // mode 3 -#define PIO_INT_ACTIVE_HIGH (1<<5) -#define PIO_INT_AND_MODE (1<<6) -#define PIO_INT_ENABLE (1<<7) +#define PIO_INT_DISABLE 0 +#define PIO_INT_ACTIVE_HIGH 2 +#define PIO_INT_AND_MODE 4 +#define PIO_INT_ENABLE 8 -/* functions used internallyto interface with the device */ +/* functions used internally to interface with the device */ inline void _pio_write(uint8_t reg, uint8_t data); inline uint8_t _pio_read(uint8_t reg); |