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authorNao Pross <naopross@thearcway.org>2017-03-17 16:19:01 +0100
committerNao Pross <naopross@thearcway.org>2017-03-17 16:19:01 +0100
commit8434120295aac533a05d274236b1506cc215705b (patch)
treebe7784133ef8e30c2150323c779bec9049a7d723 /sw
parentupdated todolist; doc: keyboard stuff (diff)
downloadz80uPC-8434120295aac533a05d274236b1506cc215705b.tar.gz
z80uPC-8434120295aac533a05d274236b1506cc215705b.zip
hardware nearly finished
doc: added datasheets for - GAL16V8 - MAX214 - MAX232 added script to build doc under windows with miktex updated notes hw: finished i/o devices and bus viewer sw: created files for pld programming
Diffstat (limited to '')
-rw-r--r--sw/pld/ADDRESS_DECODER.absbin0 -> 1481 bytes
-rw-r--r--sw/pld/ADDRESS_DECODER.jed28
-rw-r--r--sw/pld/ADDRESS_DECODER.pdf169
-rw-r--r--sw/pld/ADDRESS_DECODER.sim50
-rw-r--r--sw/pld/__Previews/ADDRESS DECODER.PLDPreview14
-rw-r--r--sw/pld/address_decoder.PLD35
6 files changed, 296 insertions, 0 deletions
diff --git a/sw/pld/ADDRESS_DECODER.abs b/sw/pld/ADDRESS_DECODER.abs
new file mode 100644
index 0000000..ab6deb9
--- /dev/null
+++ b/sw/pld/ADDRESS_DECODER.abs
Binary files differ
diff --git a/sw/pld/ADDRESS_DECODER.jed b/sw/pld/ADDRESS_DECODER.jed
new file mode 100644
index 0000000..0525a9d
--- /dev/null
+++ b/sw/pld/ADDRESS_DECODER.jed
@@ -0,0 +1,28 @@
+
+CUPL(WM) 5.0a Serial# 60008009
+Device g16v8as Library DLIB-h-40-2
+Created Fri Mar 17 15:18:30 2017
+Name ADDRESS_DECODER
+Partno 00
+Revision 01
+Date 17.03.2017
+Designer Engineer
+Company SAM Bellinzona
+Assembly None
+Location
+*QP20
+*QF2194
+*G0
+*F0
+*L00512 01110111101110111011011110111011
+*L00768 10110111101110111011011110111011
+*L01024 10111011101110111011011110111011
+*L01280 11111111111111111111111111111011
+*L01536 11111111111111111111011110111011
+*L01792 11111111111111111111101110111011
+*L02048 00000100001100000011000000100000
+*L02112 00000000110000001111111111111111
+*L02144 11111111111111111111111111111111
+*L02176 111111111111111110
+*C1E45
+*A086 \ No newline at end of file
diff --git a/sw/pld/ADDRESS_DECODER.pdf b/sw/pld/ADDRESS_DECODER.pdf
new file mode 100644
index 0000000..2a0c7dc
--- /dev/null
+++ b/sw/pld/ADDRESS_DECODER.pdf
@@ -0,0 +1,169 @@
+{COMPONENT F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER.SYM
+
+ {ENVIRONMENT
+ {PDIFvrev 3.00}
+ {Program "CUPL(WM) Version 5.0a"}
+ {DBtype "Schematic"}
+ {DBvrev 1.01}
+ {DBtime "Fri Mar 17 15:18:30 2017 "}
+ {DBunit "MIL"}
+ {DBgrid 10}
+ {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
+ "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
+ "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
+ "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+ {VIEW
+ {Mode SYMB}
+ {Nlst OPEN}
+ {Vw 0 0 2}
+ {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+ {Gs 10 10}
+ }
+ }
+
+ {DISPLAY
+ [Ly "PINNUM"]
+ [Ls "SOLID"][Wd 0]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+ {PIN_DEF
+ [Ly "PINCON"]
+ {P A8 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+ {P A9 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+ {P A10 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+ {P A11 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+ {P A12 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+ {P A13 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+ {P A14 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+ {P A15 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+ {P CSROML {Pt "I/O"}{Lq 0}{Ploc 290 20}}
+ {P CSROMH {Pt "I/O"}{Lq 0}{Ploc 290 40}}
+ {P CSRAM {Pt "I/O"}{Lq 0}{Ploc 290 60}}
+ {P CSUART {Pt "I/O"}{Lq 0}{Ploc 290 80}}
+ {P CSCTC {Pt "I/O"}{Lq 0}{Ploc 290 100}}
+ {P CSPIO {Pt "I/O"}{Lq 0}{Ploc 290 120}}
+ }
+
+ {PKG
+ [Ly "REFDES"]
+ [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+ {Rdl 195 190}
+
+ [Ly "PINNUM"]
+ [Ts 15][Tj "RC"]
+ {Pnl 120 170}
+ {Pnl 120 150}
+ {Pnl 120 130}
+ {Pnl 120 110}
+ {Pnl 120 90}
+ {Pnl 120 70}
+ {Pnl 120 50}
+ {Pnl 120 30}
+ [Ts 15][Tj "LC"]
+ {Pnl 270 30}
+ {Pnl 270 50}
+ {Pnl 270 70}
+ {Pnl 270 90}
+ {Pnl 270 110}
+ {Pnl 270 130}
+
+ {Sd A 2 3 4 5 6 7 8 9 12 13 14 15 16 17}
+ }
+
+ {PIC
+ [Ly "GATE"]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ {R 130 180 260 0}
+ {L 130 160 100 160}
+ {L 130 140 100 140}
+ {L 130 120 100 120}
+ {L 130 100 100 100}
+ {L 130 80 100 80}
+ {L 130 60 100 60}
+ {L 130 40 100 40}
+ {L 130 20 100 20}
+ {L 260 20 290 20}
+ {L 260 40 290 40}
+ {L 260 60 290 60}
+ {L 260 80 290 80}
+ {L 260 100 290 100}
+ {L 260 120 290 120}
+ [Ly "PINNAM"]
+ [Tj "LC"]
+ {T "A8" 140 160}
+ {T "A9" 140 140}
+ {T "A10" 140 120}
+ {T "A11" 140 100}
+ {T "A12" 140 80}
+ {T "A13" 140 60}
+ {T "A14" 140 40}
+ {T "A15" 140 20}
+ [Tj "RC"]
+ {T "CSROML" 250 20}
+ {T "CSROMH" 250 40}
+ {T "CSRAM" 250 60}
+ {T "CSUART" 250 80}
+ {T "CSCTC" 250 100}
+ {T "CSPIO" 250 120}
+ [Ly "DEVICE"]
+ [Tj "CT"]
+ {T "G16V8AS" 195 -10}
+ }
+
+ {ATR
+ {IN
+ {Org 100 20}
+ {Ty 255}
+ }
+ {EX
+ [Ly "ATTR2"]
+ [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+ {At PLD F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER 195 180}
+ }
+ }
+ }
+
+ {DETAIL
+ {ANNOTATE
+ }
+
+ {NET_DEF
+ {N A8
+ }
+ {N A9
+ }
+ {N A10
+ }
+ {N A11
+ }
+ {N A12
+ }
+ {N A13
+ }
+ {N A14
+ }
+ {N A15
+ }
+ {N CSROML
+ }
+ {N CSROMH
+ }
+ {N CSRAM
+ }
+ {N CSUART
+ }
+ {N CSCTC
+ }
+ {N CSPIO
+ }
+ }
+
+ {SUBCOMP
+ }
+ }
+}
diff --git a/sw/pld/ADDRESS_DECODER.sim b/sw/pld/ADDRESS_DECODER.sim
new file mode 100644
index 0000000..05661c0
--- /dev/null
+++ b/sw/pld/ADDRESS_DECODER.sim
@@ -0,0 +1,50 @@
+%SIGNAL
+PIN 2 = A8
+PIN 3 = A9
+PIN 4 = A10
+PIN 5 = A11
+PIN 6 = A12
+PIN 7 = A13
+PIN 8 = A14
+PIN 9 = A15
+PIN 16 = CSCTC
+PIN 17 = CSPIO
+PIN 14 = CSRAM
+PIN 13 = CSROMH
+PIN 12 = CSROML
+PIN 15 = CSUART
+%END
+
+%FIELD
+%END
+
+%EQUATION
+CSCTC =>
+ !A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
+
+CSPIO =>
+ A8 & A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
+
+CSRAM =>
+ !A15
+
+CSROMH =>
+ A13 & !A14 & !A15
+
+CSROML =>
+ !A13 & !A14 & !A15
+
+CSTIMER =>
+ A15
+ # A14
+ # !A13
+ # A12
+ # A11
+ # A10
+ # A9
+ # !A8
+
+CSUART =>
+ !A8 & !A9 & !A10 & !A11 & !A12 & A13 & !A14 & !A15
+
+%END
diff --git a/sw/pld/__Previews/ADDRESS DECODER.PLDPreview b/sw/pld/__Previews/ADDRESS DECODER.PLDPreview
new file mode 100644
index 0000000..8b8cb8c
--- /dev/null
+++ b/sw/pld/__Previews/ADDRESS DECODER.PLDPreview
@@ -0,0 +1,14 @@
+[Preview]
+LargeImageOriginalSize=708000
+LargeImageWidth=354
+LargeImageHeight=500
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+
diff --git a/sw/pld/address_decoder.PLD b/sw/pld/address_decoder.PLD
new file mode 100644
index 0000000..1cc9e22
--- /dev/null
+++ b/sw/pld/address_decoder.PLD
@@ -0,0 +1,35 @@
+Name ADDRESS_DECODER ;
+PartNo 00 ;
+Date 17.03.2017 ;
+Revision 01 ;
+Designer Engineer ;
+Company SAM Bellinzona ;
+Assembly None ;
+Location ;
+Device g16v8a;
+
+/* *************** INPUT PINS *********************/
+PIN 2 = A8 ;
+PIN 3 = A9 ;
+PIN 4 = A10 ;
+PIN 5 = A11 ;
+PIN 6 = A12 ;
+PIN 7 = A13 ;
+PIN 8 = A14 ;
+PIN 9 = A15 ;
+
+/* *************** OUTPUT PINS *********************/
+PIN 12 = CSROML ;
+PIN 13 = CSROMH ;
+PIN 14 = CSRAM ;
+PIN 15 = CSUART ;
+PIN 16 = CSCTC ;
+PIN 17 = CSPIO ;
+
+CSRAM = !A15 ;
+CSROML = !(!A15 & !A14 & !A13) ;
+CSROMH = !(!A15 & !A14 & A13) ;
+CSUART = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & !A9 & !A8) ;
+CSTIMER = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & !A9 & A8) ;
+CSCTC = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & A9 & !A8) ;
+CSPIO = !(!A15 & !A14 & A13 & !A12 & !A11 & !A10 & A9 & A8) ;