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diff --git a/hw-altium/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc b/hw-altium/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc
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+Protel Design System Design Rule Check
+PCB File : F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc
+Date     : 22.05.2017
+Time     : 08:35:39
+
+Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,112.559mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,113.954mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,96.229mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,94.834mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,97mm)(167.34mm,97mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,3mm)(167.34mm,3mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (167.34mm,3mm)(167.34mm,97mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,113.259mm)(-1.716mm,113.259mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,95.529mm)(-1.716mm,95.529mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(-1.016mm,119.794mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-7.016mm,96.229mm)(-7.016mm,112.559mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(11.384mm,88.994mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,119.794mm)(11.384mm,119.794mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(6.268mm,167.712mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(-2.032mm,176.712mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,176.712mm)(12.568mm,176.712mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J1" (-6.871mm,120.662mm) on Top Overlay And Board Edge 
+   Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J2" (-1.893mm,179.872mm) on Top Overlay And Board Edge 
+Rule Violations :18
+
+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.15mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.152mm) (Max=1.524mm) (Preferred=0.254mm) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.175mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45)))
+Rule Violations :0
+
+Processing Rule : Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45)))
+Rule Violations :0
+
+Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.25mm, Vertical Gap = 0.25mm ) (All),(All) 
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=0.25mm) (Max=2mm) (All)
+   Violation between Hole Size Constraint: (2.8mm > 2mm) Pad P6-34(157.24mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm
+   Violation between Hole Size Constraint: (2.8mm > 2mm) Pad P6-33(157.24mm,94.45mm) on Multi-Layer Actual Hole Size = 2.8mm
+   Violation between Hole Size Constraint: (3.26mm > 2mm) Pad J1-11(8.484mm,116.889mm) on Multi-Layer Actual Hole Size = 3.26mm
+   Violation between Hole Size Constraint: (3.26mm > 2mm) Pad J1-10(8.484mm,91.899mm) on Multi-Layer Actual Hole Size = 3.26mm
+   Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-BL(3.6mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm
+   Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-TR(157.24mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm
+   Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-TL(3.6mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm
+   Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-2(5.468mm,172.228mm) on Multi-Layer Actual Slot Hole Width = 2.54mm
+   Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-1(11.668mm,172.232mm) on Multi-Layer Actual Slot Hole Width = 2.54mm
+   Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-3(8.509mm,167.132mm) on Multi-Layer Actual Slot Hole Width = 2.54mm
+Rule Violations :10
+
+Processing Rule : Pads and Vias to follow the Drill pairs settings
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mm) (Max=25mm) (Prefered=12.5mm) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=0.35mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.08mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All)
+   Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,101.6mm)(52.324mm,101.6mm) on Top Overlay And Pad R2-1(53.34mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,101.6mm)(45.212mm,101.6mm) on Top Overlay And Pad R2-2(43.18mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,96.774mm)(52.324mm,96.774mm) on Top Overlay And Pad R1-1(53.34mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,96.774mm)(45.212mm,96.774mm) on Top Overlay And Pad R1-2(43.18mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-1(75.438mm,16.764mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-3(75.438mm,12.7mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-4(75.438mm,10.668mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-5(75.438mm,8.636mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]
+   Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.2mm) Between Text "C3" (3.848mm,135.343mm) on Top Overlay And Pad Free-TL(3.6mm,138.9mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
+Rule Violations :9
+
+Processing Rule : Silk to Silk (Clearance=0.2mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mm) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(NoConnect Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*'))
+Rule Violations :0
+
+
+Violations Detected : 37
+Time Elapsed        : 00:00:02
+\ No newline at end of file