diff options
Diffstat (limited to '')
30 files changed, 34848 insertions, 214 deletions
diff --git a/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc b/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc index 411cc1a..1b06010 100644 --- a/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc +++ b/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.drc @@ -1,115 +1,102 @@ Protel Design System Design Rule Check PCB File : F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc -Date : 19.05.2017 -Time : 14:30:28 - -WARNING: Zero hole size multi-layer pad(s) detected - Pad J2-2(215.276mil,6780.63mil) on Multi-Layer on Net DB9-5 - Pad J2-1(459.37mil,6780.787mil) on Multi-Layer on Net NetC11_2 - Pad J2-3(335mil,6580mil) on Multi-Layer on Net NetJ2_3 +Date : 22.05.2017 +Time : 08:35:39 + +Processing Rule : Board Clearance Constraint (Gap=0mm) (All) + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,112.559mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,113.954mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,96.229mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,94.834mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,97mm)(167.34mm,97mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,3mm)(167.34mm,3mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (167.34mm,3mm)(167.34mm,97mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,113.259mm)(-1.716mm,113.259mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,95.529mm)(-1.716mm,95.529mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(-1.016mm,119.794mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-7.016mm,96.229mm)(-7.016mm,112.559mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(11.384mm,88.994mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,119.794mm)(11.384mm,119.794mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(6.268mm,167.712mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(-2.032mm,176.712mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,176.712mm)(12.568mm,176.712mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J1" (-6.871mm,120.662mm) on Top Overlay And Board Edge + Violation between Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J2" (-1.893mm,179.872mm) on Top Overlay And Board Edge +Rule Violations :18 -WARNING: Multilayer Pads with 0 size Hole found - Pad J2-2(215.276mil,6780.63mil) on Multi-Layer - Pad J2-1(459.37mil,6780.787mil) on Multi-Layer - Pad J2-3(335mil,6580mil) on Multi-Layer +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 -Processing Rule : Power Plane Connect Rule(NoConnect Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*')) +Processing Rule : Clearance Constraint (Gap=0.15mm) (All),(All) Rule Violations :0 -Processing Rule : Net Antennae (Tolerance=0mil) (All) +Processing Rule : Width Constraint (Min=0.152mm) (Max=1.524mm) (Preferred=0.254mm) (All) Rule Violations :0 -Processing Rule : Silk to Silk (Clearance=7.874mil) (All),(All) - Violation between Silk To Silk Clearance Constraint: (1.733mil < 7.874mil) Between Text "16" (730mil,2490mil) on Top Overlay And Track (600mil,2500mil)(800mil,2500mil) on Top Overlay Silk Text to Silk Clearance [1.733mil] - Violation between Silk To Silk Clearance Constraint: (1.733mil < 7.874mil) Between Text "15" (630mil,2490mil) on Top Overlay And Track (600mil,2500mil)(800mil,2500mil) on Top Overlay Silk Text to Silk Clearance [1.733mil] -Rule Violations :2 +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.175mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All) +Rule Violations :0 -Processing Rule : Silk To Solder Mask (Clearance=7.874mil) (IsPad),(All) - Violation between Silk To Solder Mask Clearance Constraint: (6.537mil < 7.874mil) Between Track (420mil,6602.835mil)(494.803mil,6602.835mil) on Top Overlay And Pad J2-3(335mil,6580mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.537mil] - Violation between Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-5(2970mil,340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil] - Violation between Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-4(2970mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil] - Violation between Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-3(2970mil,500mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil] - Violation between Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-1(2970mil,660mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil] - Violation between Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (1740mil,3810mil)(1780mil,3810mil) on Top Overlay And Pad R1-2(1700mil,3810mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil] - Violation between Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (2020mil,3810mil)(2060mil,3810mil) on Top Overlay And Pad R1-1(2100mil,3810mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil] - Violation between Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (1740mil,4000mil)(1780mil,4000mil) on Top Overlay And Pad R2-2(1700mil,4000mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil] - Violation between Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (2020mil,4000mil)(2060mil,4000mil) on Top Overlay And Pad R2-1(2100mil,4000mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil] -Rule Violations :9 +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 -Processing Rule : Minimum Solder Mask Sliver (Gap=3.15mil) (All),(All) +Processing Rule : Un-Routed Net Constraint ( (All) ) Rule Violations :0 -Processing Rule : Hole To Hole Clearance (Gap=13.78mil) (All),(All) +Processing Rule : Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45))) Rule Violations :0 -Processing Rule : Height Constraint (Min=0mil) (Max=984.252mil) (Prefered=492.126mil) (All) +Processing Rule : Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45))) Rule Violations :0 -Processing Rule : Pads and Vias to follow the Drill pairs settings +Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0.25mm, Vertical Gap = 0.25mm ) (All),(All) Rule Violations :0 -Processing Rule : Hole Size Constraint (Min=9.842mil) (Max=78.74mil) (All) - Violation between Hole Size Constraint: (100mil > 78.74mil) Pad J2-3(335mil,6580mil) on Multi-Layer Actual Slot Hole Width = 100mil - Violation between Hole Size Constraint: (100mil > 78.74mil) Pad J2-1(459.37mil,6780.787mil) on Multi-Layer Actual Slot Hole Width = 100mil - Violation between Hole Size Constraint: (100mil > 78.74mil) Pad J2-2(215.276mil,6780.63mil) on Multi-Layer Actual Slot Hole Width = 100mil - Violation between Hole Size Constraint: (128.346mil > 78.74mil) Pad J1-10(334.016mil,3618.071mil) on Multi-Layer Actual Hole Size = 128.346mil - Violation between Hole Size Constraint: (128.346mil > 78.74mil) Pad J1-11(334.016mil,4601.929mil) on Multi-Layer Actual Hole Size = 128.346mil - Violation between Hole Size Constraint: (110.236mil > 78.74mil) Pad P6-33(6190.551mil,3718.504mil) on Multi-Layer Actual Hole Size = 110.236mil - Violation between Hole Size Constraint: (110.236mil > 78.74mil) Pad P6-34(6190.551mil,218.504mil) on Multi-Layer Actual Hole Size = 110.236mil -Rule Violations :7 +Processing Rule : Hole Size Constraint (Min=0.25mm) (Max=2mm) (All) + Violation between Hole Size Constraint: (2.8mm > 2mm) Pad P6-34(157.24mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm + Violation between Hole Size Constraint: (2.8mm > 2mm) Pad P6-33(157.24mm,94.45mm) on Multi-Layer Actual Hole Size = 2.8mm + Violation between Hole Size Constraint: (3.26mm > 2mm) Pad J1-11(8.484mm,116.889mm) on Multi-Layer Actual Hole Size = 3.26mm + Violation between Hole Size Constraint: (3.26mm > 2mm) Pad J1-10(8.484mm,91.899mm) on Multi-Layer Actual Hole Size = 3.26mm + Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-BL(3.6mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm + Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-TR(157.24mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm + Violation between Hole Size Constraint: (2.8mm > 2mm) Pad Free-TL(3.6mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm + Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-2(5.468mm,172.228mm) on Multi-Layer Actual Slot Hole Width = 2.54mm + Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-1(11.668mm,172.232mm) on Multi-Layer Actual Slot Hole Width = 2.54mm + Violation between Hole Size Constraint: (2.54mm > 2mm) Pad J2-3(8.509mm,167.132mm) on Multi-Layer Actual Slot Hole Width = 2.54mm +Rule Violations :10 -Processing Rule : Component Clearance Constraint ( Horizontal Gap = 9.842mil, Vertical Gap = 9.842mil ) (All),(All) +Processing Rule : Pads and Vias to follow the Drill pairs settings Rule Violations :0 -Processing Rule : Minimum Annular Ring (Minimum=6.89mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45))) +Processing Rule : Height Constraint (Min=0mm) (Max=25mm) (Prefered=12.5mm) (All) Rule Violations :0 -Processing Rule : Minimum Annular Ring (Minimum=6.89mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45))) +Processing Rule : Hole To Hole Clearance (Gap=0.35mm) (All),(All) Rule Violations :0 -Processing Rule : Un-Routed Net Constraint ( (All) ) - Violation between Un-Routed Net Constraint: Net NetC11_2 Between Pad J2-1(459.37mil,6780.787mil) on Multi-Layer And Pad C11-2(670mil,6880mil) on Multi-Layer - Violation between Un-Routed Net Constraint: Net NetC11_2 Between Pad C11-2(670mil,6880mil) on Multi-Layer And Pad U18-1(1310mil,6840mil) on Multi-Layer - Violation between Un-Routed Net Constraint: Net NetC6_1 Between Track (2000mil,4250mil)(2100mil,4150mil) on Solder Side And Pad Y1-2(2000mil,4550mil) on Multi-Layer - Violation between Un-Routed Net Constraint: Net NetC5_1 Between Pad U6-16(1700mil,3000mil) on Multi-Layer And Pad R2-2(1700mil,4000mil) on Multi-Layer -Rule Violations :4 - -Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Processing Rule : Minimum Solder Mask Sliver (Gap=0.08mm) (All),(All) Rule Violations :0 -Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=6.89mil) (Conductor Width=7.874mil) (Air Gap=7.874mil) (Entries=4) (All) -Rule Violations :0 +Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,101.6mm)(52.324mm,101.6mm) on Top Overlay And Pad R2-1(53.34mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,101.6mm)(45.212mm,101.6mm) on Top Overlay And Pad R2-2(43.18mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,96.774mm)(52.324mm,96.774mm) on Top Overlay And Pad R1-1(53.34mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,96.774mm)(45.212mm,96.774mm) on Top Overlay And Pad R1-2(43.18mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-1(75.438mm,16.764mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-3(75.438mm,12.7mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-4(75.438mm,10.668mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-5(75.438mm,8.636mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.2mm) Between Text "C3" (3.848mm,135.343mm) on Top Overlay And Pad Free-TL(3.6mm,138.9mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm] +Rule Violations :9 -Processing Rule : Width Constraint (Min=6mil) (Max=60mil) (Preferred=10mil) (All) +Processing Rule : Silk to Silk (Clearance=0.2mm) (All),(All) Rule Violations :0 -Processing Rule : Clearance Constraint (Gap=5.905mil) (All),(All) +Processing Rule : Net Antennae (Tolerance=0mm) (All) Rule Violations :0 -Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Processing Rule : Power Plane Connect Rule(NoConnect Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*')) Rule Violations :0 -Processing Rule : Board Clearance Constraint (Gap=0mil) (All) - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-67.559mil,3733.622mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-248.858mil,3788.543mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-67.559mil,4486.378mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-248.858mil,4431.457mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6957.166mil)(494.803mil,6957.166mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6602.835mil)(-80mil,6957.166mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6602.835mil)(246.772mil,6602.835mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,4716.299mil)(448.189mil,4716.299mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,3503.701mil)(448.189mil,3503.701mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-276.221mil,3788.543mil)(-276.221mil,4431.457mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,3503.701mil)(-40mil,4716.299mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-248.661mil,3760.984mil)(-67.559mil,3760.984mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-248.661mil,4459.016mil)(-67.559mil,4459.016mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6588.189mil,118.11mil)(6588.189mil,3818.898mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6229.921mil,118.11mil)(6588.189mil,118.11mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6229.921mil,3818.898mil)(6588.189mil,3818.898mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Text "J2" (-74.52mil,7081.48mil) on Top Overlay And Board Edge - Violation between Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Text "J1" (-270.52mil,4750.48mil) on Top Overlay And Board Edge -Rule Violations :18 - -Violations Detected : 40 +Violations Detected : 37 Time Elapsed : 00:00:02
\ No newline at end of file diff --git a/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.html b/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.html index 83d725b..f352e39 100644 --- a/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.html +++ b/hw/Project Outputs for z80uPC/Design Rule Check - MainBoard.html @@ -219,12 +219,12 @@ <tr class="front_matter"> <td class="front_matter_column1">Date:</td> <td class="front_matter_column2"></td> -<td class="front_matter_column3">19.05.2017</td> +<td class="front_matter_column3">22.05.2017</td> </tr> <tr class="front_matter"> <td class="front_matter_column1">Time:</td> <td class="front_matter_column2"></td> -<td class="front_matter_column3">14:30:28</td> +<td class="front_matter_column3">08:35:39</td> </tr> <tr class="front_matter"> <td class="front_matter_column1">Elapsed Time:</td> @@ -243,29 +243,21 @@ <tr> <td class="DRC_summary_header_col1">Warnings:</td> <td class="DRC_summary_header_col2"></td> -<td class="DRC_summary_header_col3" style="color : red">6</td></tr> +<td class="DRC_summary_header_col3">0</td></tr> <tr> <td class="DRC_summary_header_col1">Rule Violations:</td> <td class="DRC_summary_header_col2"></td> -<td class="DRC_summary_header_col3" style="color : red">40</td></tr> +<td class="DRC_summary_header_col3" style="color : red">37</td></tr> </table> </td> -</table><a name="IDKCST4C0TGDS3KV4VESJVF2HV3F"><h2>Summary</h2></a><table> +</table><a name="IDUFPGORCZTXPIM54UTGCQUSUSVM"><h2>Summary</h2></a><table> <tr> <th class="column1">Warnings</th> <th class="column2">Count</th> </tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDRZ4M1HPBVLM2BQ2I4ONMX444RD">Zero hole size multi-layer pad(s) detected</a></td> -<td class="column2">3</td> -</tr> -<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDORQA5XJH3JCUY2EWWPWN0XR0O">Multilayer Pads with 0 size Hole found</a></td> -<td class="column2">3</td> -</tr> <tr> <td style="font-weight : bold; text-align : right" class="column1">Total</td> -<td style="font-weight : bold" class="column2">6</td> +<td style="font-weight : bold" class="column2">0</td> </tr> </table><br><table> <tr> @@ -273,250 +265,207 @@ <th class="column2">Count</th> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#ID5QLA1KCYPMKOMWNQBOVIKGLAIE">Power Plane Connect Rule(NoConnect Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*'))</a></td> -<td class="column2">0</td> +<td class="column1"><a href="#IDAFMT0NLSLQH2RXFZXFLY5GNWN">Board Clearance Constraint (Gap=0mm) (All)</a></td> +<td class="column2">18</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDGANK14OAASEQI3NZHJNE1IDLTG">Net Antennae (Tolerance=0mil) (All)</a></td> +<td class="column1"><a href="#IDSOULDPQB2NCTCOGK4KIU2PYHYC">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDNVJ4UOARK34HB01JKLM3MOEO1N">Silk to Silk (Clearance=7.874mil) (All),(All)</a></td> -<td class="column2">2</td> +<td class="column1"><a href="#IDSFQ3SHEW4PPVDLDFA5ID5J3DH">Clearance Constraint (Gap=0.15mm) (All),(All)</a></td> +<td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#ID25OZ41T11THVDHVDHB4RED4UD">Silk To Solder Mask (Clearance=7.874mil) (IsPad),(All)</a></td> -<td class="column2">9</td> +<td class="column1"><a href="#IDFLIUKBQP1LLGDBQ22YB23ICW4B">Width Constraint (Min=0.152mm) (Max=1.524mm) (Preferred=0.254mm) (All)</a></td> +<td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDVCJ0AELTH1PSOBLRJAP0WYIMON">Minimum Solder Mask Sliver (Gap=3.15mil) (All),(All)</a></td> +<td class="column1"><a href="#IDZZ5X05QE04PCECFJABIJQGBRYO">Power Plane Connect Rule(Relief Connect )(Expansion=0.175mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDMEODJHG5IKMPE0JD13SNMLOVHN">Hole To Hole Clearance (Gap=13.78mil) (All),(All)</a></td> +<td class="column1"><a href="#IDNK5PY3KASJCMF54UGI1U2J1CSL">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDL3K1Q0QOQXDQOYVLW0L0MFJ0JK">Height Constraint (Min=0mil) (Max=984.252mil) (Prefered=492.126mil) (All)</a></td> +<td class="column1"><a href="#ID0ZKYLQHDSQLHNVJ3WMZ42LHBRP">Un-Routed Net Constraint ( (All) )</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDWHSAGFMKOUYSBLTEVPW4SMYFUI">Pads and Vias to follow the Drill pairs settings</a></td> +<td class="column1"><a href="#IDFMZJAGBTFJ1DBHKH3BLLET5XW">Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45)))</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDJSVM3G33HVFYGVS5LLMTNQR54G">Hole Size Constraint (Min=9.842mil) (Max=78.74mil) (All)</a></td> -<td class="column2">7</td> +<td class="column1"><a href="#IDKQOUEGWYTXOBECW4B4WDKEARWH">Minimum Annular Ring (Minimum=0.175mm) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45)))</a></td> +<td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#ID00S3TUG44TTKP542HXC2X2DMEE">Component Clearance Constraint ( Horizontal Gap = 9.842mil, Vertical Gap = 9.842mil ) (All),(All) </a></td> +<td class="column1"><a href="#ID2W00XDXHY2JKBGEBLDURPIVQXF">Component Clearance Constraint ( Horizontal Gap = 0.25mm, Vertical Gap = 0.25mm ) (All),(All) </a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDUS03IZ34PEWECYKNNKGKAGXW3H">Minimum Annular Ring (Minimum=6.89mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45)))</a></td> -<td class="column2">0</td> +<td class="column1"><a href="#IDXCT3U5JXRZTICDEGZLFQ3HN5KL">Hole Size Constraint (Min=0.25mm) (Max=2mm) (All)</a></td> +<td class="column2">10</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDXNAURPPKBSCJL00NSMF55XIASP">Minimum Annular Ring (Minimum=6.89mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45)))</a></td> +<td class="column1"><a href="#IDVQ3FLQ2V1FWEEZRQ4VYNWTX2PD">Pads and Vias to follow the Drill pairs settings</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDRHVJPIW3SFEHPXE2O2GUICPREH">Un-Routed Net Constraint ( (All) )</a></td> -<td class="column2">4</td> +<td class="column1"><a href="#IDX0ZUILU3SLHHD3GB2KCENYOMEG">Height Constraint (Min=0mm) (Max=25mm) (Prefered=12.5mm) (All)</a></td> +<td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDCSPOR3MPXXELJGU03OLIPDGL5">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td> +<td class="column1"><a href="#ID5QRL0C0GUZGCEWH4NAVYA1JKR">Hole To Hole Clearance (Gap=0.35mm) (All),(All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDUSJSLYJC4AMMJUB45JEXGTSMJC">Power Plane Connect Rule(Relief Connect )(Expansion=6.89mil) (Conductor Width=7.874mil) (Air Gap=7.874mil) (Entries=4) (All)</a></td> +<td class="column1"><a href="#ID24JP2FEZRZ4HB52M1ZSKQYHWAD">Minimum Solder Mask Sliver (Gap=0.08mm) (All),(All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDUH5D0FIJQZAWP1I4P053KWFKVF">Width Constraint (Min=6mil) (Max=60mil) (Preferred=10mil) (All)</a></td> -<td class="column2">0</td> +<td class="column1"><a href="#ID2ABYBXIZXDZAE5LZ0BZSH2KM3O">Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All)</a></td> +<td class="column2">9</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDIK4KZQSW2SSIFFXW0EJAG2EN1I">Clearance Constraint (Gap=5.905mil) (All),(All)</a></td> +<td class="column1"><a href="#IDLVDSHYWSKPFLDDKE0Y0YXO255N">Silk to Silk (Clearance=0.2mm) (All),(All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="#IDJBR4SJCWBC44IF555XUD2XB5GL">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td> +<td class="column1"><a href="#ID2VCULY0O43RSC4T01I2AEVTCYD">Net Antennae (Tolerance=0mm) (All)</a></td> <td class="column2">0</td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="#IDDY1ENXVOD30PFCRS4YITTZ0HM">Board Clearance Constraint (Gap=0mil) (All)</a></td> -<td class="column2">18</td> +<td class="column1"><a href="#IDUHRCRC0JOG21NBDV1BHXC0AKIH">Power Plane Connect Rule(NoConnect Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) ((ObjectKind = 'Pad') and (Name Like '*DEC*'))</a></td> +<td class="column2">0</td> </tr> <tr> <td style="font-weight : bold; text-align : right" class="column1">Total</td> -<td style="font-weight : bold" class="column2">40</td> -</tr> -</table><br><a name="IDC4AWAUAYOTWKFRYUUJ4NG3WHJL"><h2>Warnings</h2></a><a name="IDRZ4M1HPBVLM2BQ2I4ONMX444RD"><table> -<tr> -<th style="text-align : left" colspan="1" class="warning">Zero hole size multi-layer pad(s) detected</th> -</tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=10097.165mil|Location1.Y=16544.41mil|Location2.Y=16701.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=10097.165mil|Location1.Y=16544.41mil|Location2.Y=16701.89mil|Absolute=True">Pad J2-2(215.276mil,6780.63mil) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=15967.52mil|Location1.Y=9956.102mil|Location2.Y=16751.063mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=15967.52mil|Location1.Y=9956.102mil|Location2.Y=16751.063mil|Absolute=True">Net DB9-5</acronym></a></td> -</tr> -<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10341.26mil|Location1.Y=16544.567mil|Location2.Y=16702.047mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10341.26mil|Location1.Y=16544.567mil|Location2.Y=16702.047mil|Absolute=True">Pad J2-1(459.37mil,6780.787mil) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=11185.984mil|Location1.Y=16544.567mil|Location2.Y=16746.142mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=11185.984mil|Location1.Y=16544.567mil|Location2.Y=16746.142mil|Absolute=True">Net NetC11_2</acronym></a></td> +<td style="font-weight : bold" class="column2">37</td> </tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True">Pad J2-3(335mil,6580mil) on Multi-Layer</acronym></a> on <a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True">Net NetJ2_3</acronym></a></td> -</tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDORQA5XJH3JCUY2EWWPWN0XR0O"><table> +</table><br><a name="IDAFMT0NLSLQH2RXFZXFLY5GNWN"><table> <tr> -<th style="text-align : left" colspan="1" class="warning">Multilayer Pads with 0 size Hole found</th> +<th style="text-align : left" colspan="1" class="rule">Board Clearance Constraint (Gap=0mm) (All)</th> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=10097.165mil|Location1.Y=16544.41mil|Location2.Y=16701.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10018.425mil|Location2.X=10097.165mil|Location1.Y=16544.41mil|Location2.Y=16701.89mil|Absolute=True">Pad J2-2(215.276mil,6780.63mil) on Multi-Layer</acronym></a></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=14283.877mil|Location2.Y=14291.438mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=14283.877mil|Location2.Y=14291.438mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,112.559mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10341.26mil|Location1.Y=16544.567mil|Location2.Y=16702.047mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10341.26mil|Location1.Y=16544.567mil|Location2.Y=16702.047mil|Absolute=True">Pad J2-1(459.37mil,6780.787mil) on Multi-Layer</acronym></a></td> -</tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10098.78mil|Location2.X=10256.26mil|Location1.Y=16383.15mil|Location2.Y=16461.89mil|Absolute=True">Pad J2-3(335mil,6580mil) on Multi-Layer</acronym></a></td> -</tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDNVJ4UOARK34HB01JKLM3MOEO1N"><table> -<tr> -<th style="text-align : left" colspan="1" class="rule">Silk to Silk (Clearance=7.874mil) (All),(All)</th> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=14311.436mil|Location2.Y=14318.997mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=14311.436mil|Location2.Y=14318.997mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,113.954mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10567.958mil|Location2.X=10577.082mil|Location1.Y=12333.154mil|Location2.Y=12342.278mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10567.958mil|Location2.X=10577.082mil|Location1.Y=12333.154mil|Location2.Y=12342.278mil|Absolute=True">Silk To Silk Clearance Constraint: (1.733mil < 7.874mil) Between Text "16" (730mil,2490mil) on Top Overlay And Track (600mil,2500mil)(800mil,2500mil) on Top Overlay Silk Text to Silk Clearance [1.733mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=13613.601mil|Location2.Y=13621.163mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=13613.601mil|Location2.Y=13621.163mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-6.321mm,96.229mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10467.958mil|Location2.X=10477.082mil|Location1.Y=12333.154mil|Location2.Y=12342.278mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10467.958mil|Location2.X=10477.082mil|Location1.Y=12333.154mil|Location2.Y=12342.278mil|Absolute=True">Silk To Silk Clearance Constraint: (1.733mil < 7.874mil) Between Text "15" (630mil,2490mil) on Top Overlay And Track (600mil,2500mil)(800mil,2500mil) on Top Overlay Silk Text to Silk Clearance [1.733mil]</acronym></a><br></td> -</tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="ID25OZ41T11THVDHVDHB4RED4UD"><table> -<tr> -<th style="text-align : left" colspan="1" class="rule">Silk To Solder Mask (Clearance=7.874mil) (IsPad),(All)</th> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=13586.042mil|Location2.Y=13593.603mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=13586.042mil|Location2.Y=13593.603mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Arc (-1.716mm,94.834mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10250.474mil|Location2.X=10260.134mil|Location1.Y=16434.965mil|Location2.Y=16446.4mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10250.474mil|Location2.X=10260.134mil|Location1.Y=16434.965mil|Location2.Y=16446.4mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (6.537mil < 7.874mil) Between Track (420mil,6602.835mil)(494.803mil,6602.835mil) on Top Overlay And Pad J2-3(335mil,6580mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [6.537mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.707mil|Location1.Y=13657.637mil|Location2.Y=13665.198mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.707mil|Location1.Y=13657.637mil|Location2.Y=13665.198mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,97mm)(167.34mm,97mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10177.958mil|Location2.Y=10187.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10177.958mil|Location2.Y=10187.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-5(2970mil,340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.708mil|Location1.Y=9956.849mil|Location2.Y=9964.411mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.708mil|Location1.Y=9956.849mil|Location2.Y=9964.411mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (158.24mm,3mm)(167.34mm,3mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10257.958mil|Location2.Y=10267.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10257.958mil|Location2.Y=10267.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-4(2970mil,420mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16426.928mil|Location2.X=16434.489mil|Location1.Y=11807.243mil|Location2.Y=11814.804mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16426.928mil|Location2.X=16434.489mil|Location1.Y=11807.243mil|Location2.Y=11814.804mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (167.34mm,3mm)(167.34mm,97mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10337.958mil|Location2.Y=10347.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10337.958mil|Location2.Y=10347.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-3(2970mil,500mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=14297.755mil|Location2.Y=14305.316mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=14297.755mil|Location2.Y=14305.316mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,113.259mm)(-1.716mm,113.259mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10497.958mil|Location2.Y=10507.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10497.958mil|Location2.Y=10507.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (4.907mil < 7.874mil) Between Track (3010mil,250mil)(3010mil,750mil) on Top Overlay And Pad S1-1(2970mil,660mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.907mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=13599.723mil|Location2.Y=13607.285mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=13599.723mil|Location2.Y=13607.285mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-6.316mm,95.529mm)(-1.716mm,95.529mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (1740mil,3810mil)(1780mil,3810mil) on Top Overlay And Pad R1-2(1700mil,3810mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9798.739mil|Location2.X=9806.3mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9798.739mil|Location2.X=9806.3mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(-1.016mm,119.794mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (2020mil,3810mil)(2060mil,3810mil) on Top Overlay And Pad R1-1(2100mil,3810mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil]</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9562.518mil|Location2.X=9570.08mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9562.518mil|Location2.X=9570.08mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-7.016mm,96.229mm)(-7.016mm,112.559mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (1740mil,4000mil)(1780mil,4000mil) on Top Overlay And Pad R2-2(1700mil,4000mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil]</acronym></a><br></td> -</tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (7.356mil < 7.874mil) Between Track (2020mil,4000mil)(2060mil,4000mil) on Top Overlay And Pad R2-1(2100mil,4000mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.356mil]</acronym></a><br></td> -</tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDJSVM3G33HVFYGVS5LLMTNQR54G"><table> -<tr> -<th style="text-align : left" colspan="1" class="rule">Hole Size Constraint (Min=9.842mil) (Max=78.74mil) (All)</th> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=13342.44mil|Location2.Y=13350.001mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=13342.44mil|Location2.Y=13350.001mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,88.994mm)(11.384mm,88.994mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10126.895mil|Location2.X=10228.145mil|Location1.Y=16371.895mil|Location2.Y=16473.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10126.895mil|Location2.X=10228.145mil|Location1.Y=16371.895mil|Location2.Y=16473.145mil|Absolute=True">Hole Size Constraint: (100mil > 78.74mil) Pad J2-3(335mil,6580mil) on Multi-Layer Actual Slot Hole Width = 100mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=14555.038mil|Location2.Y=14562.6mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=14555.038mil|Location2.Y=14562.6mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-1.016mm,119.794mm)(11.384mm,119.794mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10251.265mil|Location2.X=10352.515mil|Location1.Y=16572.682mil|Location2.Y=16673.932mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10251.265mil|Location2.X=10352.515mil|Location1.Y=16572.682mil|Location2.Y=16673.932mil|Absolute=True">Hole Size Constraint: (100mil > 78.74mil) Pad J2-1(459.37mil,6780.787mil) on Multi-Layer Actual Slot Hole Width = 100mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16441.573mil|Location2.Y=16449.135mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16441.573mil|Location2.Y=16449.135mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(6.268mm,167.712mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10007.17mil|Location2.X=10108.42mil|Location1.Y=16572.525mil|Location2.Y=16673.775mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10007.17mil|Location2.X=10108.42mil|Location1.Y=16572.525mil|Location2.Y=16673.775mil|Absolute=True">Hole Size Constraint: (100mil > 78.74mil) Pad J2-2(215.276mil,6780.63mil) on Multi-Layer Actual Slot Hole Width = 100mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9758.739mil|Location2.X=9766.3mil|Location1.Y=16618.739mil|Location2.Y=16626.301mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9758.739mil|Location2.X=9766.3mil|Location1.Y=16618.739mil|Location2.Y=16626.301mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,167.712mm)(-2.032mm,176.712mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=13395.792mil|Location2.Y=13525.389mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=13395.792mil|Location2.Y=13525.389mil|Absolute=True">Hole Size Constraint: (128.346mil > 78.74mil) Pad J1-10(334.016mil,3618.071mil) on Multi-Layer Actual Hole Size = 128.346mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16795.905mil|Location2.Y=16803.466mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16795.905mil|Location2.Y=16803.466mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Track (-2.032mm,176.712mm)(12.568mm,176.712mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=14379.651mil|Location2.Y=14509.247mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=14379.651mil|Location2.Y=14509.247mil|Absolute=True">Hole Size Constraint: (128.346mil > 78.74mil) Pad J1-11(334.016mil,4601.929mil) on Multi-Layer Actual Hole Size = 128.346mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9608.206mil|Location2.X=9615.768mil|Location1.Y=14619.21mil|Location2.Y=14626.771mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9608.206mil|Location2.X=9615.768mil|Location1.Y=14619.21mil|Location2.Y=14626.771mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J1" (-6.871mm,120.662mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=13505.281mil|Location2.Y=13616.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=13505.281mil|Location2.Y=13616.767mil|Absolute=True">Hole Size Constraint: (110.236mil > 78.74mil) Pad P6-33(6190.551mil,3718.504mil) on Multi-Layer Actual Hole Size = 110.236mil</acronym></a><br></td> -</tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True">Hole Size Constraint: (110.236mil > 78.74mil) Pad P6-34(6190.551mil,218.504mil) on Multi-Layer Actual Hole Size = 110.236mil</acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.479mil|Location2.X=9804.04mil|Location1.Y=16950.3mil|Location2.Y=16957.862mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.479mil|Location2.X=9804.04mil|Location1.Y=16950.3mil|Location2.Y=16957.862mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 0.25mm) Between Text "J2" (-1.893mm,179.872mm) on Top Overlay And Board Edge </acronym></a><br></td> </tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDRHVJPIW3SFEHPXE2O2GUICPREH"><table> +</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDXCT3U5JXRZTICDEGZLFQ3HN5KL"><table> <tr> -<th style="text-align : left" colspan="1" class="rule">Un-Routed Net Constraint ( (All) )</th> +<th style="text-align : left" colspan="1" class="rule">Hole Size Constraint (Min=0.25mm) (Max=2mm) (All)</th> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10536.142mil|Location1.Y=16544.567mil|Location2.Y=16746.142mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10262.52mil|Location2.X=10536.142mil|Location1.Y=16544.567mil|Location2.Y=16746.142mil|Absolute=True">Un-Routed Net Constraint: Net NetC11_2 Between Pad J2-1(459.37mil,6780.787mil) on Multi-Layer And Pad C11-2(670mil,6880mil) on Multi-Layer </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True">Hole Size Constraint: (2.8mm > 2mm) Pad P6-34(157.24mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10488.898mil|Location2.X=11185.984mil|Location1.Y=16649.055mil|Location2.Y=16746.142mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10488.898mil|Location2.X=11185.984mil|Location1.Y=16649.055mil|Location2.Y=16746.142mil|Absolute=True">Un-Routed Net Constraint: Net NetC11_2 Between Pad C11-2(670mil,6880mil) on Multi-Layer And Pad U18-1(1310mil,6840mil) on Multi-Layer </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=13505.281mil|Location2.Y=13616.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=13505.281mil|Location2.Y=13616.767mil|Absolute=True">Hole Size Constraint: (2.8mm > 2mm) Pad P6-33(157.24mm,94.45mm) on Multi-Layer Actual Hole Size = 2.8mm</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11742.52mil|Location2.X=11942.52mil|Location1.Y=13992.52mil|Location2.Y=14492.52mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11742.52mil|Location2.X=11942.52mil|Location1.Y=13992.52mil|Location2.Y=14492.52mil|Absolute=True">Un-Routed Net Constraint: Net NetC6_1 Between Track (2000mil,4250mil)(2100mil,4150mil) on Solder Side And Pad Y1-2(2000mil,4550mil) on Multi-Layer </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=14379.651mil|Location2.Y=14509.247mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=14379.651mil|Location2.Y=14509.247mil|Absolute=True">Hole Size Constraint: (3.26mm > 2mm) Pad J1-11(8.484mm,116.889mm) on Multi-Layer Actual Hole Size = 3.26mm</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11512.52mil|Location2.X=11572.52mil|Location1.Y=12812.52mil|Location2.Y=13870.079mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11512.52mil|Location2.X=11572.52mil|Location1.Y=12812.52mil|Location2.Y=13870.079mil|Absolute=True">Un-Routed Net Constraint: Net NetC5_1 Between Pad U6-16(1700mil,3000mil) on Multi-Layer And Pad R2-2(1700mil,4000mil) on Multi-Layer </acronym></a><br></td> -</tr> -</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="IDDY1ENXVOD30PFCRS4YITTZ0HM"><table> -<tr> -<th style="text-align : left" colspan="1" class="rule">Board Clearance Constraint (Gap=0mil) (All)</th> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=13395.792mil|Location2.Y=13525.389mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10111.737mil|Location2.X=10241.334mil|Location1.Y=13395.792mil|Location2.Y=13525.389mil|Absolute=True">Hole Size Constraint: (3.26mm > 2mm) Pad J1-10(8.484mm,91.899mm) on Multi-Layer Actual Hole Size = 3.26mm</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=13586.042mil|Location2.Y=13593.603mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=13586.042mil|Location2.Y=13593.603mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-67.559mil,3733.622mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9928.509mil|Location2.X=10039.995mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9928.509mil|Location2.X=10039.995mil|Location1.Y=10005.281mil|Location2.Y=10116.767mil|Absolute=True">Hole Size Constraint: (2.8mm > 2mm) Pad Free-BL(3.6mm,5.55mm) on Multi-Layer Actual Hole Size = 2.8mm</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=13613.601mil|Location2.Y=13621.163mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=13613.601mil|Location2.Y=13621.163mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-248.858mil,3788.543mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=15255.281mil|Location2.Y=15366.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=15977.328mil|Location2.X=16088.814mil|Location1.Y=15255.281mil|Location2.Y=15366.767mil|Absolute=True">Hole Size Constraint: (2.8mm > 2mm) Pad Free-TR(157.24mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=14311.436mil|Location2.Y=14318.997mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9784.861mil|Location2.X=9792.423mil|Location1.Y=14311.436mil|Location2.Y=14318.997mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-67.559mil,4486.378mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9928.509mil|Location2.X=10039.995mil|Location1.Y=15255.281mil|Location2.Y=15366.767mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9928.509mil|Location2.X=10039.995mil|Location1.Y=15255.281mil|Location2.Y=15366.767mil|Absolute=True">Hole Size Constraint: (2.8mm > 2mm) Pad Free-TL(3.6mm,138.9mm) on Multi-Layer Actual Hole Size = 2.8mm</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=14283.877mil|Location2.Y=14291.438mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9576.2mil|Location2.X=9583.761mil|Location1.Y=14283.877mil|Location2.Y=14291.438mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Arc (-248.858mil,4431.457mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10007.17mil|Location2.X=10108.42mil|Location1.Y=16572.525mil|Location2.Y=16673.775mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10007.17mil|Location2.X=10108.42mil|Location1.Y=16572.525mil|Location2.Y=16673.775mil|Absolute=True">Hole Size Constraint: (2.54mm > 2mm) Pad J2-2(5.468mm,172.228mm) on Multi-Layer Actual Slot Hole Width = 2.54mm</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16795.905mil|Location2.Y=16803.466mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16795.905mil|Location2.Y=16803.466mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6957.166mil)(494.803mil,6957.166mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10251.265mil|Location2.X=10352.515mil|Location1.Y=16572.682mil|Location2.Y=16673.932mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10251.265mil|Location2.X=10352.515mil|Location1.Y=16572.682mil|Location2.Y=16673.932mil|Absolute=True">Hole Size Constraint: (2.54mm > 2mm) Pad J2-1(11.668mm,172.232mm) on Multi-Layer Actual Slot Hole Width = 2.54mm</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9758.739mil|Location2.X=9766.3mil|Location1.Y=16618.739mil|Location2.Y=16626.301mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9758.739mil|Location2.X=9766.3mil|Location1.Y=16618.739mil|Location2.Y=16626.301mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6602.835mil)(-80mil,6957.166mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10126.895mil|Location2.X=10228.145mil|Location1.Y=16371.895mil|Location2.Y=16473.145mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=10126.895mil|Location2.X=10228.145mil|Location1.Y=16371.895mil|Location2.Y=16473.145mil|Absolute=True">Hole Size Constraint: (2.54mm > 2mm) Pad J2-3(8.509mm,167.132mm) on Multi-Layer Actual Slot Hole Width = 2.54mm</acronym></a><br></td> </tr> -<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16441.573mil|Location2.Y=16449.135mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.032mil|Location2.X=9803.594mil|Location1.Y=16441.573mil|Location2.Y=16449.135mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-80mil,6602.835mil)(246.772mil,6602.835mil) on Top Overlay And Board Edge </acronym></a><br></td> -</tr> -<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=14555.038mil|Location2.Y=14562.6mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=14555.038mil|Location2.Y=14562.6mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,4716.299mil)(448.189mil,4716.299mil) on Top Overlay And Board Edge </acronym></a><br></td> +</table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br><a name="ID2ABYBXIZXDZAE5LZ0BZSH2KM3O"><table> +<tr> +<th style="text-align : left" colspan="1" class="rule">Silk To Solder Mask (Clearance=0.2mm) (IsPad),(All)</th> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=13342.44mil|Location2.Y=13350.001mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9816.608mil|Location2.X=9824.169mil|Location1.Y=13342.44mil|Location2.Y=13350.001mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,3503.701mil)(448.189mil,3503.701mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,101.6mm)(52.324mm,101.6mm) on Top Overlay And Pad R2-1(53.34mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9562.518mil|Location2.X=9570.08mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9562.518mil|Location2.X=9570.08mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-276.221mil,3788.543mil)(-276.221mil,4431.457mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13837.958mil|Location2.Y=13847.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,101.6mm)(45.212mm,101.6mm) on Top Overlay And Pad R2-2(43.18mm,101.6mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9798.739mil|Location2.X=9806.3mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9798.739mil|Location2.X=9806.3mil|Location1.Y=13948.739mil|Location2.Y=13956.3mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-40mil,3503.701mil)(-40mil,4716.299mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11906.636mil|Location2.X=11915.76mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (51.308mm,96.774mm)(52.324mm,96.774mm) on Top Overlay And Pad R1-1(53.34mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=13599.723mil|Location2.Y=13607.285mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=13599.723mil|Location2.Y=13607.285mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-248.661mil,3760.984mil)(-67.559mil,3760.984mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=11569.28mil|Location2.X=11578.404mil|Location1.Y=13647.958mil|Location2.Y=13657.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.187mm < 0.2mm) Between Track (44.196mm,96.774mm)(45.212mm,96.774mm) on Top Overlay And Pad R1-2(43.18mm,96.774mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.187mm]</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=14297.755mil|Location2.Y=14305.316mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9680.629mil|Location2.X=9688.19mil|Location1.Y=14297.755mil|Location2.Y=14305.316mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (-248.661mil,4459.016mil)(-67.559mil,4459.016mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10497.958mil|Location2.Y=10507.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10497.958mil|Location2.Y=10507.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-1(75.438mm,16.764mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16426.928mil|Location2.X=16434.489mil|Location1.Y=11807.243mil|Location2.Y=11814.804mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16426.928mil|Location2.X=16434.489mil|Location1.Y=11807.243mil|Location2.Y=11814.804mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6588.189mil,118.11mil)(6588.189mil,3818.898mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10337.958mil|Location2.Y=10347.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10337.958mil|Location2.Y=10347.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-3(75.438mm,12.7mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.708mil|Location1.Y=9956.849mil|Location2.Y=9964.411mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.708mil|Location1.Y=9956.849mil|Location2.Y=9964.411mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6229.921mil,118.11mil)(6588.189mil,118.11mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10257.958mil|Location2.Y=10267.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10257.958mil|Location2.Y=10267.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-4(75.438mm,10.668mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]</acronym></a><br></td> </tr> <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.707mil|Location1.Y=13657.637mil|Location2.Y=13665.198mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=16285.146mil|Location2.X=16292.707mil|Location1.Y=13657.637mil|Location2.Y=13665.198mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Track (6229.921mil,3818.898mil)(6588.189mil,3818.898mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10177.958mil|Location2.Y=10187.082mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=12840.504mil|Location2.X=12849.628mil|Location1.Y=10177.958mil|Location2.Y=10187.082mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (0.125mm < 0.2mm) Between Track (76.454mm,6.35mm)(76.454mm,19.05mm) on Top Overlay And Pad S1-5(75.438mm,8.636mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.125mm]</acronym></a><br></td> </tr> <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.479mil|Location2.X=9804.04mil|Location1.Y=16950.21mil|Location2.Y=16957.771mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9796.479mil|Location2.X=9804.04mil|Location1.Y=16950.21mil|Location2.Y=16957.771mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Text "J2" (-74.52mil,7081.48mil) on Top Overlay And Board Edge </acronym></a><br></td> -</tr> -<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'"> -<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9608.206mil|Location2.X=9615.768mil|Location1.Y=14619.21mil|Location2.Y=14626.771mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9608.206mil|Location2.X=9615.768mil|Location1.Y=14619.21mil|Location2.Y=14626.771mil|Absolute=True">Board Outline Clearance(Outline Edge): (Collision < 9.842mil) Between Text "J1" (-270.52mil,4750.48mil) on Top Overlay And Board Edge </acronym></a><br></td> +<td class="column1"><a href="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9987.806mil|Location2.X=9994.056mil|Location1.Y=15222.444mil|Location2.Y=15228.693mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=9987.806mil|Location2.X=9994.056mil|Location1.Y=15222.444mil|Location2.Y=15228.693mil|Absolute=True">Silk To Solder Mask Clearance Constraint: (Collision < 0.2mm) Between Text "C3" (3.848mm,135.343mm) on Top Overlay And Pad Free-TL(3.6mm,138.9mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]</acronym></a><br></td> </tr> </table></a><hr color="#EEEEEE"><a href="#top" style="font-size: 0.9em">Back to top</a><br><br></body> </html> diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard-macro.APR_LIB b/hw/Project Outputs for z80uPC/GerberX2/MainBoard-macro.APR_LIB new file mode 100644 index 0000000..23870c4 --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard-macro.APR_LIB @@ -0,0 +1,13 @@ +G04:AMPARAMS|DCode=40|XSize=129.528mil|YSize=68.898mil|CornerRadius=0mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Slot|Shape=OvalRelief|Width=7.874mil|Gap=7.874mil|Entries=4|* +%AMTHOVALD40* +21,1,0.060630,0.068898,0,0,90.0* +1,1,0.068898,0.000000,-0.030315* +1,1,0.068898,0.000000,0.030315* +21,0,0.060630,0.053150,0,0,90.0* +1,0,0.053150,0.000000,-0.030315* +1,0,0.053150,0.000000,0.030315* +4,0,4,0.002784,-0.027531,0.027143,-0.051890,0.021575,-0.057458,-0.002784,-0.033099,0.002784,-0.027531,0.0* +4,0,4,0.002784,0.033099,-0.021575,0.057458,-0.027143,0.051890,-0.002784,0.027531,0.002784,0.033099,0.0* +4,0,4,0.002784,-0.033099,-0.021575,-0.057458,-0.027143,-0.051890,-0.002784,-0.027531,0.002784,-0.033099,0.0* +4,0,4,0.002784,0.027531,0.027143,0.051890,0.021575,0.057458,-0.002784,0.033099,0.002784,0.027531,0.0* +% diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard.EXTREP b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.EXTREP new file mode 100644 index 0000000..e5a3d9e --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.EXTREP @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------------------ +Gerber File Extension Report For: MainBoard.GBR 23.05.2017 09:54:31 +------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------ +Layer Extension Layer Description +------------------------------------------------------------------------------------------ +.gbr Component Side +.gbr Ground Plane +.gbr Power Plane +.gbr Solder Side +.gbr Bottom Pad Master +.gbr Top Pad Master +.gbr Top Overlay +.gbr Top Solder +.gbr Bottom Paste +.gbr Bottom Overlay +.gbr Bottom Solder +.gbr Top Paste +.gbr Mechanical 15 +.gbr Profile +.gbr Non-plated through-hole drill file +.gbr Plated through-hole drill file +.gbr Drill Drawing +.gbr Drill Guide +------------------------------------------------------------------------------------------ diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard.REP b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.REP new file mode 100644 index 0000000..9250871 --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.REP @@ -0,0 +1,435 @@ +************************************************************* +FileName = MainBoard.GBR +AutoAperture = True +************************************************************* +Generating : Component Side + File : MainBoard_Copper_Signal_Top.gbr + + Adding Layer : Component Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D10 + D11 + D12 + D13 + D14 + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 + D38 +************************************************************* + +************************************************************* +Generating : Ground Plane + File : MainBoard_Copper_Plane_1.gbr + + Adding Layer : Ground Plane + + Adding Layer : Multi-Layer + + +Used DCodes : + D14 + D20 + D22 + D39 + D40 + D41 + D42 + D43 + D44 + D45 + D46 + D47 + D48 + D49 + D50 + D51 + D52 + D53 + D54 + D55 + D56 + D57 +************************************************************* + +************************************************************* +Generating : Power Plane + File : MainBoard_Copper_Plane_2.gbr + + Adding Layer : Power Plane + + Adding Layer : Multi-Layer + + +Used DCodes : + D14 + D20 + D22 + D39 + D41 + D42 + D43 + D44 + D46 + D47 + D48 + D49 + D51 + D52 + D53 + D54 + D55 + D56 + D57 + D58 + D59 +************************************************************* + +************************************************************* +Generating : Solder Side + File : MainBoard_Copper_Signal_Bot.gbr + + Adding Layer : Solder Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D10 + D11 + D12 + D14 + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 + D38 +************************************************************* + +************************************************************* +Generating : Bottom Pad Master + File : MainBoard_Pads_Bot.gbr + + Adding Layer : Solder Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 +************************************************************* + +************************************************************* +Generating : Top Pad Master + File : MainBoard_Pads_Top.gbr + + Adding Layer : Component Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 +************************************************************* + +************************************************************* +Generating : Top Overlay + File : MainBoard_Legend_Top.gbr + + Adding Layer : Top Overlay + + +Used DCodes : + D14 + D60 + D61 + D62 + D63 + D64 + D65 +************************************************************* + +************************************************************* +Generating : Top Solder + File : MainBoard_Soldermask_Top.gbr + + Adding Layer : Top Solder + + Adding Layer : Component Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 + D38 +************************************************************* + +************************************************************* +Generating : Bottom Paste + File : MainBoard_Paste_Bot.gbr + + Adding Layer : Bottom Paste + + Adding Layer : Solder Side + + Adding Layer : Multi-Layer + + +Used DCodes : +************************************************************* + +************************************************************* +Generating : Bottom Overlay + File : MainBoard_Legend_Bot.gbr + + Adding Layer : Bottom Overlay + + +Used DCodes : +************************************************************* + +************************************************************* +Generating : Bottom Solder + File : MainBoard_Soldermask_Bot.gbr + + Adding Layer : Bottom Solder + + Adding Layer : Solder Side + + Adding Layer : Multi-Layer + + +Used DCodes : + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + D32 + D33 + D34 + D35 + D36 + D37 + D38 +************************************************************* + +************************************************************* +Generating : Top Paste + File : MainBoard_Paste_Top.gbr + + Adding Layer : Top Paste + + Adding Layer : Component Side + + Adding Layer : Multi-Layer + + +Used DCodes : +************************************************************* + +************************************************************* +Generating : Mechanical 15 + File : MainBoard_Mechanical_15.gbr + + Adding Layer : Mechanical 15 + + +Used DCodes : + D14 +************************************************************* + +************************************************************* +Generating : Profile + File : MainBoard_Profile.gbr + + +Used DCodes : + D66 +************************************************************* + +************************************************************* +Generating : Non-plated through-hole drill file + File : MainBoard_NPTH_Drill.gbr + + +Used DCodes : +************************************************************* + +************************************************************* +Generating : Plated through-hole drill file + File : MainBoard_PTH_Drill.gbr + + +Used DCodes : + D67 + D68 + D69 + D70 + D71 + D72 + D73 + D74 + D75 + D76 + D77 + D78 + D79 + D80 + D81 + D82 + D83 + D84 + D85 +************************************************************* + +************************************************************* +Generating : Drill Drawing + File : MainBoard_Drawing_1.gbr + + Adding Drill Pair : Solder Side-Component Side + + Adding Layer : Drill Drawing + + +Used DCodes : + D87 + D88 + D89 +************************************************************* + +************************************************************* +Generating : Drill Guide + File : MainBoard_Drillmap_1.gbr + + Adding Drill Pair : Solder Side-Component Side + + Adding Layer : Drill Guide + + +Used DCodes : + D87 +************************************************************* + diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard.RUL b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.RUL new file mode 100644 index 0000000..c2c3b78 --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.RUL @@ -0,0 +1,7 @@ +DRC Rules Export File for PCB: F:\School\Lab3\projects\z80uPC\hw\MainBoard.PcbDoc +RuleKind=Clearance|RuleName=Clearance-xPP-xTP-xTT|Scope=Board|Minimum=5.91 +RuleKind=Width|RuleName=Width-xTW|Scope=Board|Minimum=6.00 +RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=0.00 +RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0 +RuleKind=MinimumAnnularRing|RuleName=Minimum IAR >0.45mm|Scope=Board|Minimum=6.89 +RuleKind=MinimumAnnularRing|RuleName=Minimum IAR <=0.45mm|Scope=Board|Minimum=6.89 diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard.apr b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.apr new file mode 100644 index 0000000..4de09b6 --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard.apr @@ -0,0 +1,79 @@ +D10 ROUNDED 10.000 10.000 0.000 LINE 0.000 +D11 ROUNDED 7.874 7.874 0.000 LINE 0.000 +D12 ROUNDED 20.000 20.000 0.000 LINE 0.000 +D13 ROUNDED 30.000 30.000 0.000 LINE 0.000 +D14 ROUNDED 10.000 10.000 0.000 LINE 0.000 +D15 ROUNDED 78.740 157.480 0.000 FLASH 0.000 +D16 ROUNDED 78.740 157.480 0.000 FLASH 90.000 +D17 ROUNDED 187.402 187.402 0.000 FLASH 0.000 +D18 RECTANGULAR 66.535 66.535 0.000 FLASH 180.000 +D19 ROUNDED 66.535 66.535 0.000 FLASH 0.000 +D20 ROUNDED 55.118 55.118 0.000 FLASH 0.000 +D21 RECTANGULAR 59.055 59.055 0.000 FLASH 0.000 +D22 ROUNDED 59.055 59.055 0.000 FLASH 0.000 +D23 ROUNDED 47.244 47.244 0.000 FLASH 0.000 +D24 ROUNDED 72.835 72.835 0.000 FLASH 0.000 +D25 RECTANGULAR 72.835 72.835 0.000 FLASH 180.000 +D26 RECTANGULAR 59.055 59.055 0.000 FLASH 0.000 +D27 ROUNDED 59.055 59.055 0.000 FLASH 0.000 +D28 ROUNDED 60.000 60.000 0.000 FLASH 0.000 +D29 RECTANGULAR 60.000 60.000 0.000 FLASH 270.000 +D30 RECTANGULAR 59.055 59.055 0.000 FLASH 270.000 +D31 RECTANGULAR 59.055 59.055 0.000 FLASH 90.000 +D32 ROUNDED 64.961 64.961 0.000 FLASH 0.000 +D33 ROUNDED 181.102 181.102 0.000 FLASH 0.000 +D34 RECTANGULAR 64.961 64.961 0.000 FLASH 270.000 +D35 RECTANGULAR 66.929 66.929 0.000 FLASH 0.000 +D36 ROUNDED 66.929 66.929 0.000 FLASH 0.000 +D37 ROUNDED 181.102 181.102 0.000 FLASH 0.000 +D38 ROUNDED 33.465 33.465 0.000 FLASH 0.000 +D39 ROUNDED 40.000 40.000 0.000 LINE 0.000 +D41 ROUNDED 119.685 59.055 0.000 FLASH 90.000 +D42 ROUNDED 119.685 59.055 0.000 FLASH 180.000 +D43 ROUNDED 148.031 148.031 0.000 FLASH 0.000 +D44 ROUNDED 62.598 62.598 0.000 FLASH 0.000 +D45 RELIEF 72.441 72.441 0.000 FLASH 7.874 7.874 4 0.000 +D46 ROUNDED 53.150 53.150 0.000 FLASH 0.000 +D47 RELIEF 61.024 61.024 0.000 FLASH 7.874 7.874 4 0.000 +D48 ROUNDED 51.181 51.181 0.000 FLASH 0.000 +D49 ROUNDED 62.992 62.992 0.000 FLASH 0.000 +D50 RELIEF 72.835 72.835 0.000 FLASH 7.874 7.874 4 0.000 +D51 ROUNDED 55.118 55.118 0.000 FLASH 0.000 +D52 RELIEF 64.961 64.961 0.000 FLASH 7.874 7.874 4 0.000 +D53 RELIEF 64.961 64.961 0.000 FLASH 7.874 7.874 4 0.000 +D54 ROUNDED 129.921 129.921 0.000 FLASH 0.000 +D55 RELIEF 68.898 68.898 0.000 FLASH 7.874 7.874 4 0.000 +D56 ROUNDED 129.921 129.921 0.000 FLASH 0.000 +D57 ROUNDED 39.370 39.370 0.000 FLASH 0.000 +D58 ROUNDED 119.685 59.055 0.000 FLASH 90.000 +D59 RELIEF 62.992 62.992 0.000 FLASH 7.874 7.874 4 0.000 +D60 ROUNDED 7.874 7.874 0.000 LINE 0.000 +D61 ROUNDED 9.842 9.842 0.000 LINE 0.000 +D62 ROUNDED 23.622 23.622 0.000 LINE 0.000 +D63 ROUNDED 5.905 5.905 0.000 LINE 0.000 +D64 ROUNDED 8.000 8.000 0.000 LINE 0.000 +D65 RECTANGULAR 31.496 74.803 0.000 FLASH 0.000 +D66 ROUNDED 1.000 1.000 0.000 LINE 0.000 +D67 ROUNDED 100.000 39.370 0.000 FLASH 90.000 +D68 ROUNDED 100.000 39.370 0.000 FLASH 90.000 +D69 ROUNDED 100.000 39.370 0.000 FLASH 180.000 +D70 ROUNDED 128.346 128.346 0.000 FLASH 90.000 +D71 ROUNDED 42.913 42.913 0.000 FLASH 180.000 +D72 ROUNDED 33.465 33.465 0.000 FLASH 0.000 +D73 ROUNDED 35.433 35.433 0.000 FLASH 0.000 +D74 ROUNDED 31.496 31.496 0.000 FLASH 0.000 +D75 ROUNDED 43.307 43.307 0.000 FLASH 180.000 +D76 ROUNDED 31.496 31.496 0.000 FLASH 270.000 +D77 ROUNDED 35.433 35.433 0.000 FLASH 0.000 +D78 ROUNDED 35.433 35.433 0.000 FLASH 270.000 +D79 ROUNDED 35.433 35.433 0.000 FLASH 90.000 +D80 ROUNDED 39.370 39.370 0.000 FLASH 90.000 +D81 ROUNDED 110.236 110.236 0.000 FLASH 90.000 +D82 ROUNDED 110.236 110.236 0.000 FLASH 0.000 +D83 ROUNDED 110.236 110.236 0.000 FLASH 0.000 +D84 ROUNDED 110.236 110.236 0.000 FLASH 0.000 +D85 ROUNDED 19.685 19.685 0.000 FLASH 0.000 +D86 ROUNDED 5.000 5.000 0.000 LINE 0.000 +D87 ROUNDED 5.000 5.000 0.000 LINE 0.000 +D88 ROUNDED 6.667 6.667 0.000 LINE 0.000 +D89 ROUNDED 4.000 4.000 0.000 LINE 0.000 diff --git a/hw/Project Outputs for z80uPC/GerberX2/MainBoard_Copper_Plane_1.gbr b/hw/Project Outputs for z80uPC/GerberX2/MainBoard_Copper_Plane_1.gbr new file mode 100644 index 0000000..3e62b1a --- /dev/null +++ b/hw/Project Outputs for z80uPC/GerberX2/MainBoard_Copper_Plane_1.gbr @@ -0,0 +1,1905 @@ +G04 Layer_Physical_Order=2* +G04 Layer_Color=32768* +%FSLAX26Y26*% +%MOIN*% +%TF.FileFunction,Copper,L2,Inr,Plane*% +%TF.Part,Single*% +G01* +G75* +%TA.AperFunction,NonConductor*% +%ADD14C,0.010000*% +%TA.AperFunction,ComponentPad*% +%ADD20C,0.055118*% +%ADD22C,0.059055*% +%TA.AperFunction,NonConductor*% +%ADD39C,0.040000*% +%TA.AperFunction,ComponentPad*% +%AMTHOVALD40* +21,1,0.060630,0.068898,0,0,90.0* +1,1,0.068898,0.000000,-0.030315* +1,1,0.068898,0.000000,0.030315* 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+ diff --git a/hw/Project Outputs for z80uPC/Status Report.Txt b/hw/Project Outputs for z80uPC/Status Report.Txt index 6b5e7df..3cf8803 100644 --- a/hw/Project Outputs for z80uPC/Status Report.Txt +++ b/hw/Project Outputs for z80uPC/Status Report.Txt @@ -1,10 +1,34 @@ -Output: Protel -Type : ProtelNetlist -From : Project [z80uPC.PrjPCB] - Generated File[MainSheet.NET] +Project Outputs Generation Report +--------------------------------- +Start Output Generation At 09:54:31 On 23.05.2017 +Output: Gerber X2 Files +Type : GerberX2 +From : PCB Document [MainBoard.PcbDoc] + Generated File[MainBoard_Copper_Signal_Top.gbr] + Generated File[MainBoard_Copper_Plane_1.gbr] + Generated File[MainBoard_Copper_Plane_2.gbr] + Generated File[MainBoard_Copper_Signal_Bot.gbr] + Generated File[MainBoard_Pads_Bot.gbr] + Generated File[MainBoard_Pads_Top.gbr] + Generated File[MainBoard_Legend_Top.gbr] + Generated File[MainBoard_Soldermask_Top.gbr] + Generated File[MainBoard_Paste_Bot.gbr] + Generated File[MainBoard_Legend_Bot.gbr] + Generated File[MainBoard_Soldermask_Bot.gbr] + Generated File[MainBoard_Paste_Top.gbr] + Generated File[MainBoard_Mechanical_15.gbr] + Generated File[MainBoard_Profile.gbr] + Generated File[MainBoard_NPTH_Drill.gbr] + Generated File[MainBoard_PTH_Drill.gbr] + Generated File[MainBoard_Drawing_1.gbr] + Generated File[MainBoard_Drillmap_1.gbr] + Generated File[MainBoard.RUL] + Generated File[MainBoard.EXTREP] + Generated File[MainBoard.REP] -Files Generated : 1 + +Files Generated : 21 Documents Printed : 0 -Finished Output Generation At 10:54:34 On 06.03.2017 +Finished Output Generation At 09:54:33 On 23.05.2017 diff --git a/hw/Project Outputs for z80uPC/Z80uPC_GerberX2.zip b/hw/Project Outputs for z80uPC/Z80uPC_GerberX2.zip Binary files differnew file mode 100644 index 0000000..871c9c4 --- /dev/null +++ b/hw/Project Outputs for z80uPC/Z80uPC_GerberX2.zip diff --git a/hw/Project Outputs for z80uPC/z80uPC.pdf b/hw/Project Outputs for z80uPC/z80uPC.pdf Binary files differindex 9e0cf37..aebf27e 100644 --- a/hw/Project Outputs for z80uPC/z80uPC.pdf +++ b/hw/Project Outputs for z80uPC/z80uPC.pdf diff --git a/hw/Project Outputs for z80uPC/z80uPC_PCB.pdf b/hw/Project Outputs for z80uPC/z80uPC_PCB.pdf Binary files differindex bb6eb9a..d27b454 100644 --- a/hw/Project Outputs for z80uPC/z80uPC_PCB.pdf +++ b/hw/Project Outputs for z80uPC/z80uPC_PCB.pdf |