diff options
Diffstat (limited to '')
| -rw-r--r-- | hw/z80uPC.PrjPCB | 102 |
1 files changed, 54 insertions, 48 deletions
diff --git a/hw/z80uPC.PrjPCB b/hw/z80uPC.PrjPCB index acee579..b1b3b06 100644 --- a/hw/z80uPC.PrjPCB +++ b/hw/z80uPC.PrjPCB @@ -1313,6 +1313,10 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId= +[GeneratedDocument1] +DocumentPath=Project Outputs for z80uPC\MainSheet.NET +DItemRevisionGUID= + [SearchPath1] Path=F:\Programs\Altium16\libraries\*.* IncludeSubFolders=1 @@ -1332,63 +1336,65 @@ Name=Netlist Outputs Description= TargetPrinter=Brother MFC-L8650CDW Printer PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 -OutputType1=CadnetixNetlist -OutputName1=Cadnetix Netlist +OutputType1=SciCardsNetlist +OutputName1=SciCards Netlist OutputDocumentPath1= OutputVariantName1= OutputDefault1=0 -OutputType2=CalayNetlist -OutputName2=Calay Netlist +OutputType2=TangoNetlist +OutputName2=Tango Netlist OutputDocumentPath2= OutputVariantName2= OutputDefault2=0 -OutputType3=EDIF -OutputName3=EDIF for PCB +OutputType3=TelesisNetlist +OutputName3=Telesis Netlist OutputDocumentPath3= OutputVariantName3= OutputDefault3=0 -OutputType4=EESofNetlist -OutputName4=EESof Netlist +OutputType4=ProtelNetlist +OutputName4=Protel OutputDocumentPath4= OutputVariantName4= OutputDefault4=0 -OutputType5=IntergraphNetlist -OutputName5=Intergraph Netlist +Configuration4_Name1=OutputConfigurationParameter1 +Configuration4_Item1=NetlistVersion=0|Record=ProtelNetlistView +OutputType5=RacalNetlist +OutputName5=Racal Netlist OutputDocumentPath5= OutputVariantName5= OutputDefault5=0 -OutputType6=MentorBoardStationNetlist -OutputName6=Mentor BoardStation Netlist +OutputType6=RINFNetlist +OutputName6=RINF Netlist OutputDocumentPath6= OutputVariantName6= OutputDefault6=0 -OutputType7=MultiWire -OutputName7=MultiWire +OutputType7=XSpiceNetlist +OutputName7=XSpice Netlist OutputDocumentPath7= OutputVariantName7= OutputDefault7=0 -OutputType8=OrCadPCB2Netlist -OutputName8=Orcad/PCB2 Netlist +OutputType8=SIMetrixNetlist +OutputName8=SIMetrix OutputDocumentPath8= OutputVariantName8= OutputDefault8=0 -OutputType9=PADSNetlist -OutputName9=PADS ASCII Netlist +OutputType9=SIMPLISNetlist +OutputName9=SIMPLIS OutputDocumentPath9= OutputVariantName9= OutputDefault9=0 -OutputType10=Pcad -OutputName10=Pcad for PCB +OutputType10=Verilog +OutputName10=Verilog File OutputDocumentPath10= OutputVariantName10= OutputDefault10=0 -OutputType11=PCADNetlist -OutputName11=PCAD Netlist +OutputType11=VHDL +OutputName11=VHDL File OutputDocumentPath11= OutputVariantName11= OutputDefault11=0 -OutputType12=PCADnltNetlist -OutputName12=PCADnlt Netlist +OutputType12=WireListNetlist +OutputName12=WireList Netlist OutputDocumentPath12= OutputVariantName12= OutputDefault12=0 @@ -1397,63 +1403,63 @@ OutputName13=Protel2 Netlist OutputDocumentPath13= OutputVariantName13= OutputDefault13=0 -OutputType14=ProtelNetlist -OutputName14=Protel +OutputType14=EESofNetlist +OutputName14=EESof Netlist OutputDocumentPath14= OutputVariantName14= OutputDefault14=0 -OutputType15=RacalNetlist -OutputName15=Racal Netlist +OutputType15=IntergraphNetlist +OutputName15=Intergraph Netlist OutputDocumentPath15= OutputVariantName15= OutputDefault15=0 -OutputType16=RINFNetlist -OutputName16=RINF Netlist +OutputType16=MentorBoardStationNetlist +OutputName16=Mentor BoardStation Netlist OutputDocumentPath16= OutputVariantName16= OutputDefault16=0 -OutputType17=SciCardsNetlist -OutputName17=SciCards Netlist +OutputType17=CadnetixNetlist +OutputName17=Cadnetix Netlist OutputDocumentPath17= OutputVariantName17= OutputDefault17=0 -OutputType18=TangoNetlist -OutputName18=Tango Netlist +OutputType18=CalayNetlist +OutputName18=Calay Netlist OutputDocumentPath18= OutputVariantName18= OutputDefault18=0 -OutputType19=TelesisNetlist -OutputName19=Telesis Netlist +OutputType19=EDIF +OutputName19=EDIF for PCB OutputDocumentPath19= OutputVariantName19= OutputDefault19=0 -OutputType20=Verilog -OutputName20=Verilog File +OutputType20=Pcad +OutputName20=Pcad for PCB OutputDocumentPath20= OutputVariantName20= OutputDefault20=0 -OutputType21=VHDL -OutputName21=VHDL File +OutputType21=PCADNetlist +OutputName21=PCAD Netlist OutputDocumentPath21= OutputVariantName21= OutputDefault21=0 -OutputType22=WireListNetlist -OutputName22=WireList Netlist +OutputType22=PCADnltNetlist +OutputName22=PCADnlt Netlist OutputDocumentPath22= OutputVariantName22= OutputDefault22=0 -OutputType23=XSpiceNetlist -OutputName23=XSpice Netlist +OutputType23=MultiWire +OutputName23=MultiWire OutputDocumentPath23= OutputVariantName23= OutputDefault23=0 -OutputType24=SIMetrixNetlist -OutputName24=SIMetrix +OutputType24=OrCadPCB2Netlist +OutputName24=Orcad/PCB2 Netlist OutputDocumentPath24= OutputVariantName24= OutputDefault24=0 -OutputType25=SIMPLISNetlist -OutputName25=SIMPLIS +OutputType25=PADSNetlist +OutputName25=PADS ASCII Netlist OutputDocumentPath25= OutputVariantName25= OutputDefault25=0 |