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-rwxr-xr-xsw/cpld/address_decoder.out437
1 files changed, 437 insertions, 0 deletions
diff --git a/sw/cpld/address_decoder.out b/sw/cpld/address_decoder.out
new file mode 100755
index 0000000..163d8a9
--- /dev/null
+++ b/sw/cpld/address_decoder.out
@@ -0,0 +1,437 @@
+
+19 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 CSRAM 0 0 0 -1 -1 2 0 21
+ 83 CSPIO 0 0 0 -1 -1 1 0 21
+ 82 CSCTC 0 1 0 -1 -1 1 0 21
+ 81 CSUART 0 0 0 -1 -1 1 0 21
+ 79 CSROML 0 1 0 -1 -1 1 0 21
+ 78 CSROMH 0 1 0 -1 -1 1 0 21
+ 93 PA_5_ 1 -1 -1 2 0 1 -1 -1
+ 92 PA_6_ 1 -1 -1 2 0 1 -1 -1
+ 91 PA_7_ 1 -1 -1 2 0 1 -1 -1
+ 90 PA_8_ 1 -1 -1 2 0 1 -1 -1
+ 89 PA_9_ 1 -1 -1 2 0 1 -1 -1
+ 88 PA_10_ 1 -1 -1 2 0 1 -1 -1
+ 87 PA_11_ 1 -1 -1 2 0 1 -1 -1
+ 86 PA_12_ 1 -1 -1 2 0 1 -1 -1
+ 85 PA_13_ 1 -1 -1 2 0 1 -1 -1
+ 84 PA_14_ 1 -1 -1 2 0 1 -1 -1
+ 77 PA_15_ 1 -1 -1 2 0 1 -1 -1
+ 95 PA_3_ 1 -1 -1 1 0 -1 -1
+ 94 PA_4_ 1 -1 -1 1 0 -1 -1
+19 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 CSRAM 0 0 0 -1 -1 2 0 21
+ 83 CSPIO 0 0 0 -1 -1 1 0 21
+ 82 CSCTC 0 1 0 -1 -1 1 0 21
+ 81 CSUART 0 0 0 -1 -1 1 0 21
+ 79 CSROML 0 1 0 -1 -1 1 0 21
+ 78 CSROMH 0 1 0 -1 -1 1 0 21
+ 93 PA_5_ 1 -1 -1 2 0 1 -1 -1
+ 92 PA_6_ 1 -1 -1 2 0 1 -1 -1
+ 91 PA_7_ 1 -1 -1 2 0 1 -1 -1
+ 90 PA_8_ 1 -1 -1 2 0 1 -1 -1
+ 89 PA_9_ 1 -1 -1 2 0 1 -1 -1
+ 88 PA_10_ 1 -1 -1 2 0 1 -1 -1
+ 87 PA_11_ 1 -1 -1 2 0 1 -1 -1
+ 86 PA_12_ 1 -1 -1 2 0 1 -1 -1
+ 85 PA_13_ 1 -1 -1 2 0 1 -1 -1
+ 84 PA_14_ 1 -1 -1 2 0 1 -1 -1
+ 77 PA_15_ 1 -1 -1 2 0 1 -1 -1
+ 95 PA_3_ 1 -1 -1 1 0 -1 -1
+ 94 PA_4_ 1 -1 -1 1 0 -1 -1
+22 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 PA_15_ 1 -1 -1 1 1 20 -1
+ 19 PA_14_ 1 -1 -1 1 1 19 -1
+ 18 PA_13_ 1 -1 -1 1 1 18 -1
+ 17 PA_12_ 1 -1 -1 1 1 17 -1
+ 16 PA_11_ 1 -1 -1 1 1 16 -1
+ 15 PA_10_ 1 -1 -1 1 1 15 -1
+ 14 PA_9_ 1 -1 -1 1 1 14 -1
+ 13 PA_8_ 1 -1 -1 1 1 13 -1
+ 8 PA_0_ 1 -1 -1 1 1 8 -1
+ 7 PA_1_ 1 -1 -1 1 1 7 -1
+ 6 PA_2_ 1 -1 -1 1 1 6 -1
+ 5 PA_3_ 1 -1 -1 1 1 5 -1
+ 4 PA_4_ 1 -1 -1 1 1 4 -1
+ 3 PA_5_ 1 -1 -1 1 1 3 -1
+ 2 PA_6_ 1 -1 -1 1 1 2 -1
+ 1 PA_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+18 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+25 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+ 77 IORQ 1 -1 -1 1 1 -1 -1
+25 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 30 IORQ 1 -1 -1 1 1 30 -1
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+21 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+ 77 IORQ 1 -1 -1 1 1 -1 -1
+21 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 29 IORQ 1 -1 -1 1 1 29 -1
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1 \ No newline at end of file
generated by cgit v1.2.1 (git 2.18.0) at 2024-11-14 10:33:40 +0100