1 files changed, 0 insertions, 136 deletions
diff --git a/sw/cpld/address_decoder.vcl b/sw/cpld/address_decoder.vcl
deleted file mode 100755
index 6befbd2..0000000
--- a/sw/cpld/address_decoder.vcl
+++ /dev/null
@@ -1,136 +0,0 @@
-[DEVICE]
-
-Family = M4;
-PartType = M4-32/32;
-Package = 44PLCC;
-PartNumber = M4-32/32-15JC;
-Speed = -15;
-Operating_condition = COM;
-EN_Segment = NO;
-Pin_MC_1to1 = NO;
-Voltage = 5.0;
-
-[REVISION]
-
-RCS = "$Revision: 1.24 $";
-Parent = m4.vci;
-SDS_file = m4.sds;
-Design = address_decoder.tt4;
-Rev = 0.01;
-DATE = 11/23/17;
-TIME = 11:55:45;
-Type = TT2;
-Pre_Fit_Time = 1;
-Source_Format = ABEL_Schematic;
-
-[IGNORE ASSIGNMENTS]
-
-Pin_Assignments = NO;
-Pin_Keep_Block = NO;
-Pin_Keep_Segment = NO;
-Group_Assignments = NO;
-Macrocell_Assignments = NO;
-Macrocell_Keep_Block = NO;
-Macrocell_Keep_Segment = NO;
-Pin_Reservation = NO;
-Timing_Constraints = NO;
-Block_Reservation = NO;
-Segment_Reservation = NO;
-Ignore_Source_Location = NO;
-Ignore_Source_Optimization = NO;
-Ignore_Source_Timing = NO;
-
-[CLEAR ASSIGNMENTS]
-
-Pin_Assignments = NO;
-Pin_Keep_Block = NO;
-Pin_Keep_Segment = NO;
-Group_Assignments = NO;
-Macrocell_Assignments = NO;
-Macrocell_Keep_Block = NO;
-Macrocell_Keep_Segment = NO;
-Pin_Reservation = NO;
-Timing_Constraints = NO;
-Block_Reservation = NO;
-Segment_Reservation = NO;
-Ignore_Source_Location = NO;
-Ignore_Source_Optimization = NO;
-Ignore_Source_Timing = NO;
-
-[BACKANNOTATE NETLIST]
-
-Netlist = VHDL;
-Delay_File = SDF;
-Generic_VCC = ;
-Generic_GND = ;
-
-[BACKANNOTATE ASSIGNMENTS]
-
-Pin_Assignment = NO;
-Pin_Block = NO;
-Pin_Macrocell_Block = NO;
-Routing = NO;
-
-[GLOBAL PROJECT OPTIMIZATION]
-
-Balanced_Partitioning = YES;
-Spread_Placement = YES;
-Max_Pin_Percent = 100;
-Max_Macrocell_Percent = 100;
-Max_Inter_Seg_Percent = 100;
-Max_Seg_In_Percent = 100;
-Max_Blk_In_Percent = 100;
-
-[FITTER REPORT FORMAT]
-
-Fitter_Options = YES;
-Pinout_Diagram = NO;
-Pinout_Listing = YES;
-Detailed_Block_Segment_Summary = YES;
-Input_Signal_List = YES;
-Output_Signal_List = YES;
-Bidir_Signal_List = YES;
-Node_Signal_List = YES;
-Signal_Fanout_List = YES;
-Block_Segment_Fanin_List = YES;
-Prefit_Eqn = YES;
-Postfit_Eqn = YES;
-Page_Break = YES;
-
-[OPTIMIZATION OPTIONS]
-
-Logic_Reduction = YES;
-Max_PTerm_Split = 16;
-Max_PTerm_Collapse = 16;
-XOR_Synthesis = YES;
-Node_Collapse = Yes;
-DT_Synthesis = Yes;
-
-[FITTER GLOBAL OPTIONS]
-
-Run_Time = 0;
-Set_Reset_Dont_Care = NO;
-In_Reg_Optimize = YES;
-Clock_Optimize = NO;
-Conf_Unused_IOs = OUT_LOW;
-
-[POWER]
-
-[HARDWARE DEVICE OPTIONS]
-
-[PIN RESERVATIONS]
-layer = OFF;
-
-[LOCATION ASSIGNMENT]
-
-Layer = OFF
-MMU_OUT_12_ = OUTPUT,39,1,-;
-MMU_OUT_13_ = OUTPUT,38,1,-;
-MMU_OUT_14_ = OUTPUT,37,1,-;
-MMU_OUT_15_ = OUTPUT,36,1,-;
-CSPIO = OUTPUT,29,1,-;
-CSCTC = OUTPUT,28,1,-;
-CSUART = OUTPUT,27,1,-;
-CSRAM = OUTPUT,26,1,-;
-CSROMH = OUTPUT,25,1,-;
-CSROML = OUTPUT,24,1,-;