diff options
Diffstat (limited to '')
95 files changed, 5521 insertions, 1348 deletions
diff --git a/sw/cpld/ADDRESS_DECODER.STY b/sw/cpld/ADDRESS_DECODER.STY deleted file mode 100644 index afd24c5..0000000 --- a/sw/cpld/ADDRESS_DECODER.STY +++ /dev/null @@ -1,4 +0,0 @@ -[STRATEGY-LIST] -Normal=True, 1491209776 -[synthesis-type] -tool=Synplify diff --git a/sw/cpld/ADDRESS_DECODER.TCL b/sw/cpld/ADDRESS_DECODER.TCL new file mode 100755 index 0000000..e83cb1f --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.TCL @@ -0,0 +1,37 @@ +#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file .\ADDRESS_DECODER.TCL
+#-- Written on Thu Nov 23 11:54:33 2017
+
+
+#-- begin a new section
+project -new
+
+#-- Device options
+set_option -technology mach
+
+#-- add_file options
+add_file -vhdl -lib work "address_decoder.vhd"
+
+#-- top module name
+set_option -top_module ADDRESS_DECODER
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#-- set result format/file last
+project -result_file "ADDRESS_DECODER.edi"
+
+#-- error message log file
+project -log_file ADDRESS_DECODER.log
+
+#-- let's save it
+project -save ADDRESS_DECODER.tc_
+
+#-- run Synplify
+project -run
+
+#-- **************************************************
+
+#-- exit from Synplify
+exit
diff --git a/sw/cpld/ADDRESS_DECODER.abt b/sw/cpld/ADDRESS_DECODER.abt new file mode 100755 index 0000000..8d21960 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.abt @@ -0,0 +1,62 @@ +
+
+MODULE ADDRESS_DECODER
+
+" TOOL: vhdl2tf
+" DATE: 11/23/17 11:54:50
+" TITLE: Lattice Semiconductor Corporation
+" MODULE: ADDRESS_DECODER
+" DESIGN: ADDRESS_DECODER
+" FILENAME: ADDRESS_DECODER.abt
+" PROJECT: address_decoder
+" VERSION: 1.0
+" NOTE: DO NOT EDIT THIS FILE DIRECTLY.
+" This file is auto generated by ispDesignEXPERT System.
+" It can be removed or overwritten automatically.
+" If you want to edit this file, copy it to another file or
+" rename it with different file extension first.
+
+
+" Inputs
+ MMU_IN_15_ pin;
+ MMU_IN_14_ pin;
+ MMU_IN_13_ pin;
+ MMU_IN_12_ pin;
+ MMU_IN_11_ pin;
+ MMU_IN_10_ pin;
+ MMU_IN_9_ pin;
+ MMU_IN_8_ pin;
+ MMU_IN_7_ pin;
+ MMU_IN_6_ pin;
+ MMU_IN_5_ pin;
+ MMU_IN_4_ pin;
+ MMU_IN_3_ pin;
+ MMU_IN_2_ pin;
+ MMU_IN_1_ pin;
+ MMU_IN_0_ pin;
+ IORQ pin;
+ RD pin;
+
+
+" Outputs
+ MMU_OUT_15_ pin;
+ MMU_OUT_14_ pin;
+ MMU_OUT_13_ pin;
+ MMU_OUT_12_ pin;
+ CSROML pin;
+ CSROMH pin;
+ CSRAM pin;
+ CSUART pin;
+ CSCTC pin;
+ CSPIO pin;
+
+
+" Bidirs
+
+
+
+Test_vectors
+([MMU_IN_15_,MMU_IN_14_,MMU_IN_13_,MMU_IN_12_,MMU_IN_11_,MMU_IN_10_,MMU_IN_9_,MMU_IN_8_,MMU_IN_7_,MMU_IN_6_,MMU_IN_5_,MMU_IN_4_,MMU_IN_3_,MMU_IN_2_,MMU_IN_1_,MMU_IN_0_,IORQ,RD] -> [MMU_OUT_15_,MMU_OUT_14_,MMU_OUT_13_,MMU_OUT_12_,CSROML,CSROMH,CSRAM,CSUART,CSCTC,CSPIO])
+
+
+END
diff --git a/sw/cpld/ADDRESS_DECODER.bl0 b/sw/cpld/ADDRESS_DECODER.bl0 new file mode 100755 index 0000000..6c4f5d5 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.bl0 @@ -0,0 +1,107 @@ +#$ DATE Thu Nov 23 11:54:43 2017
+#$ TOOL Edif2Blif version 8.2
+#$ MODULE address_decoder
+#$ PINS 28 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ IORQ MMU_IN_2_ RD MMU_IN_1_ CSROML MMU_IN_0_ CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_11_ MMU_IN_10_ MMU_IN_9_ MMU_IN_8_
+#$ NODES 34 op_ge_un24_csromh op_lt_un11_csromh un12_csromhZ0 N_117 N_181 op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0
+MMU_IN_i_0_7 MMU_IN_i_0_6 MMU_IN_i_0_5 MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 MMU_IN_c_3 MMU_IN_c_4
+MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 MMU_IN_c_c_12 MMU_IN_c_c_13 MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c un12_csromh_i_c
+MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.model address_decoder
+.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF MMU_IN_12_.BLIF MMU_IN_11_.BLIF MMU_IN_10_.BLIF MMU_IN_9_.BLIF MMU_IN_8_.BLIF \
+ MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF MMU_IN_3_.BLIF MMU_IN_2_.BLIF MMU_IN_1_.BLIF MMU_IN_0_.BLIF op_ge_un24_csromh.BLIF \
+ op_lt_un11_csromh.BLIF un12_csromhZ0.BLIF N_117.BLIF N_181.BLIF op_lt_un11_cspio.BLIF N_56.BLIF N_54.BLIF N_51.BLIF IORQ_iZ0.BLIF \
+ MMU_IN_i_0_7.BLIF MMU_IN_i_0_6.BLIF MMU_IN_i_0_5.BLIF MMU_IN_i_0_3.BLIF MMU_IN_i_0_2.BLIF MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF MMU_IN_c_2.BLIF MMU_IN_c_3.BLIF \
+ MMU_IN_c_4.BLIF MMU_IN_c_5.BLIF MMU_IN_c_6.BLIF MMU_IN_c_7.BLIF MMU_IN_c_c_12.BLIF MMU_IN_c_c_13.BLIF MMU_IN_c_c_14.BLIF MMU_IN_c_c_15.BLIF IORQ_c.BLIF \
+ op_ge_un24_csromh_i_c.BLIF un12_csromh_i_c.BLIF MMU_IN_i_c_15.BLIF N_181_i_0_c.BLIF GND.BLIF N_184.BLIF
+.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ MMU_OUT_13_ MMU_OUT_12_ op_ge_un24_csromh \
+ op_lt_un11_csromh un12_csromhZ0 N_117 N_181 op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0 MMU_IN_i_0_7 MMU_IN_i_0_6 \
+ MMU_IN_i_0_5 MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 MMU_IN_c_3 MMU_IN_c_4 MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 \
+ MMU_IN_c_c_12 MMU_IN_c_c_13 MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c un12_csromh_i_c MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.names MMU_IN_2_.BLIF MMU_IN_c_2
+1 1
+.names MMU_IN_3_.BLIF MMU_IN_c_3
+1 1
+.names MMU_IN_4_.BLIF MMU_IN_c_4
+1 1
+.names MMU_IN_5_.BLIF MMU_IN_c_5
+1 1
+.names MMU_IN_6_.BLIF MMU_IN_c_6
+1 1
+.names MMU_IN_7_.BLIF MMU_IN_c_7
+1 1
+.names MMU_IN_12_.BLIF MMU_IN_c_c_12
+1 1
+.names MMU_IN_13_.BLIF MMU_IN_c_c_13
+1 1
+.names MMU_IN_14_.BLIF MMU_IN_c_c_14
+1 1
+.names MMU_IN_15_.BLIF MMU_IN_c_c_15
+1 1
+.names MMU_IN_c_c_12.BLIF MMU_OUT_12_
+1 1
+.names MMU_IN_c_c_13.BLIF MMU_OUT_13_
+1 1
+.names MMU_IN_c_c_14.BLIF MMU_OUT_14_
+1 1
+.names MMU_IN_c_c_15.BLIF MMU_OUT_15_
+1 1
+.names IORQ.BLIF IORQ_c
+1 1
+.names op_ge_un24_csromh_i_c.BLIF CSROML
+1 1
+.names un12_csromh_i_c.BLIF CSROMH
+1 1
+.names MMU_IN_i_c_15.BLIF CSRAM
+1 1
+.names GND.BLIF CSUART
+1 1
+.names GND.BLIF CSCTC
+1 1
+.names N_181_i_0_c.BLIF CSPIO
+1 1
+.names op_lt_un11_cspio.BLIF N_184.BLIF N_181
+11 1
+.names MMU_IN_c_4.BLIF IORQ_iZ0.BLIF N_184
+11 1
+.names MMU_IN_c_6.BLIF MMU_IN_i_0_6
+0 1
+.names MMU_IN_c_5.BLIF MMU_IN_i_0_5
+0 1
+.names MMU_IN_c_3.BLIF MMU_IN_i_0_3
+0 1
+.names MMU_IN_c_2.BLIF MMU_IN_i_0_2
+0 1
+.names MMU_IN_c_c_14.BLIF MMU_IN_i_0_14
+0 1
+.names MMU_IN_c_c_13.BLIF MMU_IN_i_0_13
+0 1
+.names op_lt_un11_csromh.BLIF op_ge_un24_csromh_i_c.BLIF un12_csromhZ0
+11 1
+.names MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF N_117
+11 1
+.names MMU_IN_i_c_15.BLIF N_117.BLIF op_ge_un24_csromh
+11 1
+.names MMU_IN_i_c_15.BLIF MMU_IN_i_0_14.BLIF op_lt_un11_csromh
+11 1
+.names MMU_IN_i_0_3.BLIF MMU_IN_i_0_2.BLIF N_51
+11 1
+.names N_51.BLIF MMU_IN_i_0_5.BLIF N_54
+11 1
+.names N_54.BLIF MMU_IN_i_0_6.BLIF N_56
+11 1
+.names N_56.BLIF MMU_IN_i_0_7.BLIF op_lt_un11_cspio
+11 1
+.names N_181.BLIF N_181_i_0_c
+0 1
+.names MMU_IN_c_c_15.BLIF MMU_IN_i_c_15
+0 1
+.names un12_csromhZ0.BLIF un12_csromh_i_c
+0 1
+.names op_ge_un24_csromh.BLIF op_ge_un24_csromh_i_c
+0 1
+.names IORQ_c.BLIF IORQ_iZ0
+0 1
+.names MMU_IN_c_7.BLIF MMU_IN_i_0_7
+0 1
+.names GND
+.end
diff --git a/sw/cpld/ADDRESS_DECODER.bl1 b/sw/cpld/ADDRESS_DECODER.bl1 new file mode 100755 index 0000000..b5f7d35 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.bl1 @@ -0,0 +1,142 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE address_decoder
+#$ PINS 28 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ \
+# IORQ MMU_IN_2_ RD MMU_IN_1_ CSROML MMU_IN_0_ CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART \
+# MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_11_ MMU_IN_10_ \
+# MMU_IN_9_ MMU_IN_8_
+#$ NODES 34 op_ge_un24_csromh op_lt_un11_csromh un12_csromhZ0 N_117 N_181 \
+# op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0 MMU_IN_i_0_7 MMU_IN_i_0_6 MMU_IN_i_0_5 \
+# MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 MMU_IN_c_3 \
+# MMU_IN_c_4 MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 MMU_IN_c_c_12 MMU_IN_c_c_13 \
+# MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c un12_csromh_i_c \
+# MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.model address_decoder
+.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF \
+MMU_IN_12_.BLIF MMU_IN_11_.BLIF MMU_IN_10_.BLIF MMU_IN_9_.BLIF MMU_IN_8_.BLIF \
+MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF MMU_IN_3_.BLIF \
+MMU_IN_2_.BLIF MMU_IN_1_.BLIF MMU_IN_0_.BLIF op_ge_un24_csromh.BLIF \
+op_lt_un11_csromh.BLIF un12_csromhZ0.BLIF N_117.BLIF N_181.BLIF \
+op_lt_un11_cspio.BLIF N_56.BLIF N_54.BLIF N_51.BLIF IORQ_iZ0.BLIF \
+MMU_IN_i_0_7.BLIF MMU_IN_i_0_6.BLIF MMU_IN_i_0_5.BLIF MMU_IN_i_0_3.BLIF \
+MMU_IN_i_0_2.BLIF MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF MMU_IN_c_2.BLIF \
+MMU_IN_c_3.BLIF MMU_IN_c_4.BLIF MMU_IN_c_5.BLIF MMU_IN_c_6.BLIF \
+MMU_IN_c_7.BLIF MMU_IN_c_c_12.BLIF MMU_IN_c_c_13.BLIF MMU_IN_c_c_14.BLIF \
+MMU_IN_c_c_15.BLIF IORQ_c.BLIF op_ge_un24_csromh_i_c.BLIF un12_csromh_i_c.BLIF \
+MMU_IN_i_c_15.BLIF N_181_i_0_c.BLIF GND.BLIF N_184.BLIF
+.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ \
+MMU_OUT_13_ MMU_OUT_12_ op_ge_un24_csromh op_lt_un11_csromh un12_csromhZ0 \
+N_117 N_181 op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0 MMU_IN_i_0_7 MMU_IN_i_0_6 \
+MMU_IN_i_0_5 MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 \
+MMU_IN_c_3 MMU_IN_c_4 MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 MMU_IN_c_c_12 \
+MMU_IN_c_c_13 MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c \
+un12_csromh_i_c MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.names MMU_IN_i_c_15.BLIF N_117.BLIF op_ge_un24_csromh
+11 1
+.names MMU_IN_i_c_15.BLIF MMU_IN_i_0_14.BLIF op_lt_un11_csromh
+11 1
+.names op_lt_un11_csromh.BLIF op_ge_un24_csromh_i_c.BLIF un12_csromhZ0
+11 1
+.names MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF N_117
+11 1
+.names op_lt_un11_cspio.BLIF N_184.BLIF N_181
+11 1
+.names N_56.BLIF MMU_IN_i_0_7.BLIF op_lt_un11_cspio
+11 1
+.names N_54.BLIF MMU_IN_i_0_6.BLIF N_56
+11 1
+.names N_51.BLIF MMU_IN_i_0_5.BLIF N_54
+11 1
+.names MMU_IN_i_0_3.BLIF MMU_IN_i_0_2.BLIF N_51
+11 1
+.names IORQ_c.BLIF IORQ_iZ0
+0 1
+.names MMU_IN_c_7.BLIF MMU_IN_i_0_7
+0 1
+.names MMU_IN_c_6.BLIF MMU_IN_i_0_6
+0 1
+.names MMU_IN_c_5.BLIF MMU_IN_i_0_5
+0 1
+.names MMU_IN_c_3.BLIF MMU_IN_i_0_3
+0 1
+.names MMU_IN_c_2.BLIF MMU_IN_i_0_2
+0 1
+.names MMU_IN_c_c_14.BLIF MMU_IN_i_0_14
+0 1
+.names MMU_IN_c_c_13.BLIF MMU_IN_i_0_13
+0 1
+.names op_ge_un24_csromh.BLIF op_ge_un24_csromh_i_c
+0 1
+.names un12_csromhZ0.BLIF un12_csromh_i_c
+0 1
+.names MMU_IN_c_c_15.BLIF MMU_IN_i_c_15
+0 1
+.names N_181.BLIF N_181_i_0_c
+0 1
+.names GND
+.names MMU_IN_c_4.BLIF IORQ_iZ0.BLIF N_184
+11 1
+.names MMU_IN_c_c_15.BLIF MMU_OUT_15_
+1 1
+0 0
+.names op_ge_un24_csromh_i_c.BLIF CSROML
+1 1
+0 0
+.names un12_csromh_i_c.BLIF CSROMH
+1 1
+0 0
+.names MMU_IN_i_c_15.BLIF CSRAM
+1 1
+0 0
+.names GND.BLIF CSUART
+1 1
+0 0
+.names GND.BLIF CSCTC
+1 1
+0 0
+.names N_181_i_0_c.BLIF CSPIO
+1 1
+0 0
+.names MMU_IN_c_c_14.BLIF MMU_OUT_14_
+1 1
+0 0
+.names MMU_IN_c_c_13.BLIF MMU_OUT_13_
+1 1
+0 0
+.names MMU_IN_c_c_12.BLIF MMU_OUT_12_
+1 1
+0 0
+.names MMU_IN_2_.BLIF MMU_IN_c_2
+1 1
+0 0
+.names MMU_IN_3_.BLIF MMU_IN_c_3
+1 1
+0 0
+.names MMU_IN_4_.BLIF MMU_IN_c_4
+1 1
+0 0
+.names MMU_IN_5_.BLIF MMU_IN_c_5
+1 1
+0 0
+.names MMU_IN_6_.BLIF MMU_IN_c_6
+1 1
+0 0
+.names MMU_IN_7_.BLIF MMU_IN_c_7
+1 1
+0 0
+.names MMU_IN_12_.BLIF MMU_IN_c_c_12
+1 1
+0 0
+.names MMU_IN_13_.BLIF MMU_IN_c_c_13
+1 1
+0 0
+.names MMU_IN_14_.BLIF MMU_IN_c_c_14
+1 1
+0 0
+.names MMU_IN_15_.BLIF MMU_IN_c_c_15
+1 1
+0 0
+.names IORQ.BLIF IORQ_c
+1 1
+0 0
+.end
diff --git a/sw/cpld/ADDRESS_DECODER.eq0 b/sw/cpld/ADDRESS_DECODER.eq0 new file mode 100755 index 0000000..a63d155 --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.eq0 @@ -0,0 +1,193 @@ +Edif2Blif version 8.2
+
+Design address_decoder created Thu Nov 23 11:54:43 2017
+
+
+ P-Terms Fan-in Fan-out Type Name (attributes)
+--------- ------ ------- ---- -----------------
+ 1/1 1 1 Pin MMU_OUT_15_
+ 1/1 1 1 Pin CSROML
+ 1/1 1 1 Pin CSROMH
+ 1/1 1 1 Pin MMU_OUT_14_
+ 1/1 1 1 Pin CSRAM
+ 1/1 1 1 Pin MMU_OUT_13_
+ 1/1 1 1 Pin CSUART
+ 1/1 1 1 Pin MMU_OUT_12_
+ 1/1 1 1 Pin CSCTC
+ 1/1 1 1 Pin CSPIO
+ 1 2 1 Node op_ge_un24_csromh
+ 1 2 1 Node op_lt_un11_csromh
+ 1 2 1 Node un12_csromhZ0
+ 1 2 1 Node N_117
+ 1 2 1 Node N_181
+ 1 2 1 Node op_lt_un11_cspio
+ 1 2 1 Node N_56
+ 1 2 1 Node N_54
+ 1 2 1 Node N_51
+ 1 1 1 Node IORQ_iZ0
+ 1 1 1 Node MMU_IN_i_0_7
+ 1 1 1 Node MMU_IN_i_0_6
+ 1 1 1 Node MMU_IN_i_0_5
+ 1 1 1 Node MMU_IN_i_0_3
+ 1 1 1 Node MMU_IN_i_0_2
+ 1 1 1 Node MMU_IN_i_0_14
+ 1 1 1 Node MMU_IN_i_0_13
+ 1/1 1 1 Node MMU_IN_c_2
+ 1/1 1 1 Node MMU_IN_c_3
+ 1/1 1 1 Node MMU_IN_c_4
+ 1/1 1 1 Node MMU_IN_c_5
+ 1/1 1 1 Node MMU_IN_c_6
+ 1/1 1 1 Node MMU_IN_c_7
+ 1/1 1 1 Node MMU_IN_c_c_12
+ 1/1 1 1 Node MMU_IN_c_c_13
+ 1/1 1 1 Node MMU_IN_c_c_14
+ 1/1 1 1 Node MMU_IN_c_c_15
+ 1/1 1 1 Node IORQ_c
+ 1 1 1 Node op_ge_un24_csromh_i_c
+ 1 1 1 Node un12_csromh_i_c
+ 1 1 1 Node MMU_IN_i_c_15
+ 1 1 1 Node N_181_i_0_c
+ 0 0 1 Node GND
+ 1 2 1 Node N_184
+=========
+ 43/21 Best P-Term Total: 43
+ Total Pins: 28
+ Total Nodes: 34
+ Average P-Term/Output: 0
+
+
+Equations:
+
+MMU_OUT_15_ = (MMU_IN_c_c_15);
+
+CSROML = (op_ge_un24_csromh_i_c);
+
+CSROMH = (un12_csromh_i_c);
+
+MMU_OUT_14_ = (MMU_IN_c_c_14);
+
+CSRAM = (MMU_IN_i_c_15);
+
+MMU_OUT_13_ = (MMU_IN_c_c_13);
+
+CSUART = (GND);
+
+MMU_OUT_12_ = (MMU_IN_c_c_12);
+
+CSCTC = (GND);
+
+CSPIO = (N_181_i_0_c);
+
+op_ge_un24_csromh = (MMU_IN_i_c_15 & N_117);
+
+op_lt_un11_csromh = (MMU_IN_i_c_15 & MMU_IN_i_0_14);
+
+un12_csromhZ0 = (op_lt_un11_csromh & op_ge_un24_csromh_i_c);
+
+N_117 = (MMU_IN_i_0_14 & MMU_IN_i_0_13);
+
+N_181 = (op_lt_un11_cspio & N_184);
+
+op_lt_un11_cspio = (N_56 & MMU_IN_i_0_7);
+
+N_56 = (N_54 & MMU_IN_i_0_6);
+
+N_54 = (N_51 & MMU_IN_i_0_5);
+
+N_51 = (MMU_IN_i_0_3 & MMU_IN_i_0_2);
+
+IORQ_iZ0 = (!IORQ_c);
+
+MMU_IN_i_0_7 = (!MMU_IN_c_7);
+
+MMU_IN_i_0_6 = (!MMU_IN_c_6);
+
+MMU_IN_i_0_5 = (!MMU_IN_c_5);
+
+MMU_IN_i_0_3 = (!MMU_IN_c_3);
+
+MMU_IN_i_0_2 = (!MMU_IN_c_2);
+
+MMU_IN_i_0_14 = (!MMU_IN_c_c_14);
+
+MMU_IN_i_0_13 = (!MMU_IN_c_c_13);
+
+MMU_IN_c_2 = (MMU_IN_2_);
+
+MMU_IN_c_3 = (MMU_IN_3_);
+
+MMU_IN_c_4 = (MMU_IN_4_);
+
+MMU_IN_c_5 = (MMU_IN_5_);
+
+MMU_IN_c_6 = (MMU_IN_6_);
+
+MMU_IN_c_7 = (MMU_IN_7_);
+
+MMU_IN_c_c_12 = (MMU_IN_12_);
+
+MMU_IN_c_c_13 = (MMU_IN_13_);
+
+MMU_IN_c_c_14 = (MMU_IN_14_);
+
+MMU_IN_c_c_15 = (MMU_IN_15_);
+
+IORQ_c = (IORQ);
+
+op_ge_un24_csromh_i_c = (!op_ge_un24_csromh);
+
+un12_csromh_i_c = (!un12_csromhZ0);
+
+MMU_IN_i_c_15 = (!MMU_IN_c_c_15);
+
+N_181_i_0_c = (!N_181);
+
+GND = (0);
+
+N_184 = (MMU_IN_c_4 & IORQ_iZ0);
+
+
+Reverse-Polarity Equations:
+
+!MMU_OUT_15_ = (!MMU_IN_c_c_15);
+
+!CSROML = (!op_ge_un24_csromh_i_c);
+
+!CSROMH = (!un12_csromh_i_c);
+
+!MMU_OUT_14_ = (!MMU_IN_c_c_14);
+
+!CSRAM = (!MMU_IN_i_c_15);
+
+!MMU_OUT_13_ = (!MMU_IN_c_c_13);
+
+!CSUART = (!GND);
+
+!MMU_OUT_12_ = (!MMU_IN_c_c_12);
+
+!CSCTC = (!GND);
+
+!CSPIO = (!N_181_i_0_c);
+
+!MMU_IN_c_2 = (!MMU_IN_2_);
+
+!MMU_IN_c_3 = (!MMU_IN_3_);
+
+!MMU_IN_c_4 = (!MMU_IN_4_);
+
+!MMU_IN_c_5 = (!MMU_IN_5_);
+
+!MMU_IN_c_6 = (!MMU_IN_6_);
+
+!MMU_IN_c_7 = (!MMU_IN_7_);
+
+!MMU_IN_c_c_12 = (!MMU_IN_12_);
+
+!MMU_IN_c_c_13 = (!MMU_IN_13_);
+
+!MMU_IN_c_c_14 = (!MMU_IN_14_);
+
+!MMU_IN_c_c_15 = (!MMU_IN_15_);
+
+!IORQ_c = (!IORQ);
+
diff --git a/sw/cpld/ADDRESS_DECODER.exf b/sw/cpld/ADDRESS_DECODER.exf new file mode 100755 index 0000000..02c560b --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.exf @@ -0,0 +1,33 @@ +Section Type Array Num Name Real Name Base Number Increment
+// -------------------------------------------------------------------------------------------------
+ Port 1 MMU_IN(15:0) MMU_IN 15 16 -1
+ Port 2 MMU_OUT(15:12) MMU_OUT 15 4 -1
+End
+Section Member Rename Array-Notation Array Number Index
+// -------------------------------------------------------------------------------------
+ Port MMU_IN_15_ MMU_IN[15] 1 0
+ Port MMU_IN_14_ MMU_IN[14] 1 1
+ Port MMU_IN_13_ MMU_IN[13] 1 2
+ Port MMU_IN_12_ MMU_IN[12] 1 3
+ Port MMU_IN_11_ MMU_IN[11] 1 4
+ Port MMU_IN_10_ MMU_IN[10] 1 5
+ Port MMU_IN_9_ MMU_IN[9] 1 6
+ Port MMU_IN_8_ MMU_IN[8] 1 7
+ Port MMU_IN_7_ MMU_IN[7] 1 8
+ Port MMU_IN_6_ MMU_IN[6] 1 9
+ Port MMU_IN_5_ MMU_IN[5] 1 10
+ Port MMU_IN_4_ MMU_IN[4] 1 11
+ Port MMU_IN_3_ MMU_IN[3] 1 12
+ Port MMU_IN_2_ MMU_IN[2] 1 13
+ Port MMU_IN_1_ MMU_IN[1] 1 14
+ Port MMU_IN_0_ MMU_IN[0] 1 15
+ Port MMU_OUT_15_ MMU_OUT[15] 2 0
+ Port MMU_OUT_14_ MMU_OUT[14] 2 1
+ Port MMU_OUT_13_ MMU_OUT[13] 2 2
+ Port MMU_OUT_12_ MMU_OUT[12] 2 3
+End
+Section Cross Reference File
+Design 'ADDRESS_DECODER' created Thu Nov 23 11:54:43 2017
+ Type New Name Original Name
+// ----------------------------------------------------------------------
+End
diff --git a/sw/cpld/ADDRESS_DECODER.lci b/sw/cpld/ADDRESS_DECODER.lci deleted file mode 100644 index 47875d5..0000000 --- a/sw/cpld/ADDRESS_DECODER.lci +++ /dev/null @@ -1,107 +0,0 @@ - -[Device] -Family = M4A3; -PartNumber = M4A3-32/32-10JC; -Package = 44PLCC; -PartType = M4A3-32/32; -Speed = -10; -Operating_condition = COM; -Status = Production; - -[Revision] -Parent = m4a332.lci; -DATE = 2002; -TIME = 0:00:00; -Source_Format = Pure_VHDL; -Synthesis = Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -layer = OFF; - -[Group Assignments] -layer = OFF; - -[Resource Reservations] -layer = OFF; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] -NetList = VHDL; - -[IO Types] -layer = OFF; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - -[opt global constraints list] - -[Explorer User Settings] - -[Pin attributes list] - -[global constraints list] - -[Global Constraints Process Update] - -[pin lock limitation] - -[LOCATION ASSIGNMENTS LIST] - -[RESOURCE RESERVATIONS LIST] - -[individual constraints list] - -[Attributes list setting] - -[Timing Analyzer] - -[PLL Assignments] - -[Dual Function Macrocell] - -[Explorer Results] - -[VHDL synplify constraints] - -[VHDL spectrum constraints] - -[verilog synplify constraints] - -[verilog spectrum constraints] - -[VHDL synplify constraints list] - -[VHDL spectrum constraints list] - -[verilog synplify constraints list] - -[verilog spectrum constraints list] diff --git a/sw/cpld/ADDRESS_DECODER.lct b/sw/cpld/ADDRESS_DECODER.lct deleted file mode 100644 index 47875d5..0000000 --- a/sw/cpld/ADDRESS_DECODER.lct +++ /dev/null @@ -1,107 +0,0 @@ - -[Device] -Family = M4A3; -PartNumber = M4A3-32/32-10JC; -Package = 44PLCC; -PartType = M4A3-32/32; -Speed = -10; -Operating_condition = COM; -Status = Production; - -[Revision] -Parent = m4a332.lci; -DATE = 2002; -TIME = 0:00:00; -Source_Format = Pure_VHDL; -Synthesis = Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -layer = OFF; - -[Group Assignments] -layer = OFF; - -[Resource Reservations] -layer = OFF; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] -NetList = VHDL; - -[IO Types] -layer = OFF; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - -[opt global constraints list] - -[Explorer User Settings] - -[Pin attributes list] - -[global constraints list] - -[Global Constraints Process Update] - -[pin lock limitation] - -[LOCATION ASSIGNMENTS LIST] - -[RESOURCE RESERVATIONS LIST] - -[individual constraints list] - -[Attributes list setting] - -[Timing Analyzer] - -[PLL Assignments] - -[Dual Function Macrocell] - -[Explorer Results] - -[VHDL synplify constraints] - -[VHDL spectrum constraints] - -[verilog synplify constraints] - -[verilog spectrum constraints] - -[VHDL synplify constraints list] - -[VHDL spectrum constraints list] - -[verilog synplify constraints list] - -[verilog spectrum constraints list] diff --git a/sw/cpld/ADDRESS_DECODER.naf b/sw/cpld/ADDRESS_DECODER.naf index fe52855..08db701 100644..100755 --- a/sw/cpld/ADDRESS_DECODER.naf +++ b/sw/cpld/ADDRESS_DECODER.naf @@ -1,22 +1,28 @@ -PA[15] i -PA[14] i -PA[13] i -PA[12] i -PA[11] i -PA[10] i -PA[9] i -PA[8] i -PA[7] i -PA[6] i -PA[5] i -PA[4] i -PA[3] i -PA[2] i -PA[1] i -PA[0] i -CSROMH o -CSROML o -CSRAM o -CSUART o -CSCTC o -CSPIO o +MMU_IN[15] i
+MMU_IN[14] i
+MMU_IN[13] i
+MMU_IN[12] i
+MMU_IN[11] i
+MMU_IN[10] i
+MMU_IN[9] i
+MMU_IN[8] i
+MMU_IN[7] i
+MMU_IN[6] i
+MMU_IN[5] i
+MMU_IN[4] i
+MMU_IN[3] i
+MMU_IN[2] i
+MMU_IN[1] i
+MMU_IN[0] i
+MMU_OUT[15] o
+MMU_OUT[14] o
+MMU_OUT[13] o
+MMU_OUT[12] o
+IORQ i
+RD i
+CSROML o
+CSROMH o
+CSRAM o
+CSUART o
+CSCTC o
+CSPIO o
diff --git a/sw/cpld/ADDRESS_DECODER.syn b/sw/cpld/ADDRESS_DECODER.syn deleted file mode 100644 index 419b6ba..0000000 --- a/sw/cpld/ADDRESS_DECODER.syn +++ /dev/null @@ -1,11 +0,0 @@ -JDF B -// Created by Version 2.0 -PROJECT ADDRESS_DECODER -DESIGN address_decoder Normal -DEVKIT M4A3-32/32-10JC -ENTRY Pure VHDL -MODULE address_decoder.vhd -MODSTYLE ADDRESS_DECODER Normal -SYNTHESIS_TOOL Synplify -SIMULATOR_TOOL ActiveHDL -TOPMODULE ADDRESS_DECODER diff --git a/sw/cpld/ADDRESS_DECODER.tcl b/sw/cpld/ADDRESS_DECODER.tcl deleted file mode 100644 index 4c9fe3f..0000000 --- a/sw/cpld/ADDRESS_DECODER.tcl +++ /dev/null @@ -1,270 +0,0 @@ - -########## Tcl recorder starts at 04/03/17 14:05:56 ########## - -set version "2.0" -set proj_dir "//nas001/account_PIF/_prossn/SAMB_3/lab3/projects/z80uPC/sw/cpld" -cd $proj_dir - -# Get directory paths -set pver $version -regsub -all {\.} $pver {_} pver -set lscfile "lsc_" -append lscfile $pver ".ini" -set lsvini_dir [lindex [array get env LSC_INI_PATH] 1] -set lsvini_path [file join $lsvini_dir $lscfile] -if {[catch {set fid [open $lsvini_path]} msg]} { - puts "File Open Error: $lsvini_path" - return false -} else {set data [read $fid]; close $fid } -foreach line [split $data '\n'] { - set lline [string tolower $line] - set lline [string trim $lline] - if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue} - if {$path && [regexp {^\[} $lline]} {set path 0; break} - if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue} - if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue} - if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}} - -set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end] -regsub -all "\"" $cpld_bin "" cpld_bin -set cpld_bin [file join $cpld_bin] -set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]] -regsub -all "\"" $install_dir "" install_dir -set install_dir [file join $install_dir] -set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end] -regsub -all "\"" $fpga_dir "" fpga_dir -set fpga_dir [file join $fpga_dir] -set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end] -regsub -all "\"" $fpga_bin "" fpga_bin -set fpga_bin [file join $fpga_bin] - -if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } { - set env(PATH) "$fpga_bin;$env(PATH)" } - -if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } { - set env(PATH) "$cpld_bin;$env(PATH)" } - -lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"] -package require runcmd - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:05:56 ########### - - -########## Tcl recorder starts at 04/03/17 14:07:59 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:07:59 ########### - - -########## Tcl recorder starts at 04/03/17 14:08:48 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:08:48 ########### - - -########## Tcl recorder starts at 04/03/17 14:11:44 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:11:44 ########### - - -########## Tcl recorder starts at 04/03/17 14:22:22 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:22:22 ########### - - -########## Tcl recorder starts at 04/03/17 14:22:30 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:22:31 ########### - - -########## Tcl recorder starts at 04/03/17 14:28:11 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:28:11 ########### - - -########## Tcl recorder starts at 04/03/17 14:56:18 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:56:18 ########### - - -########## Tcl recorder starts at 04/03/17 14:56:23 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/03/17 14:56:23 ########### - - -########## Tcl recorder starts at 04/13/17 10:29:16 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/13/17 10:29:16 ########### - - -########## Tcl recorder starts at 04/13/17 10:29:50 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/13/17 10:29:50 ########### - - -########## Tcl recorder starts at 04/13/17 10:33:10 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/13/17 10:33:10 ########### - - -########## Tcl recorder starts at 04/13/17 10:33:11 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/13/17 10:33:11 ########### - - -########## Tcl recorder starts at 04/13/17 10:34:43 ########## - -# Commands to make the Process: -# Hierarchy -if [runCmd "\"$cpld_bin/vhd2jhd\" address_decoder.vhd -o address_decoder.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { - return -} else { - vwait done - if [checkResult $done] { - return - } -} - -########## Tcl recorder end at 04/13/17 10:34:43 ########### - diff --git a/sw/cpld/ADDRESS_DECODER.vht b/sw/cpld/ADDRESS_DECODER.vht new file mode 100755 index 0000000..9894b9f --- /dev/null +++ b/sw/cpld/ADDRESS_DECODER.vht @@ -0,0 +1,76 @@ +
+-- VHDL Test Bench Created from source file ADDRESS_DECODER.vhd -- 11/23/17 11:54:48
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Lattice recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "source->import"
+-- menu in the ispDesignExpert System Project Navigator to import the testbench.
+-- Then edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+LIBRARY generics;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE generics.components.ALL;
+
+ENTITY testbench IS
+END testbench;
+
+ARCHITECTURE behavior OF testbench IS
+
+ COMPONENT ADDRESS_DECODER
+ PORT(
+ MMU_IN : IN std_logic_vector(15 downto 0);
+ IORQ : IN std_logic;
+ RD : IN std_logic;
+ MMU_OUT : OUT std_logic_vector(15 downto 12);
+ CSROML : OUT std_logic;
+ CSROMH : OUT std_logic;
+ CSRAM : OUT std_logic;
+ CSUART : OUT std_logic;
+ CSCTC : OUT std_logic;
+ CSPIO : OUT std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL MMU_IN : std_logic_vector(15 downto 0);
+ SIGNAL MMU_OUT : std_logic_vector(15 downto 12);
+ SIGNAL IORQ : std_logic;
+ SIGNAL RD : std_logic;
+ SIGNAL CSROML : std_logic;
+ SIGNAL CSROMH : std_logic;
+ SIGNAL CSRAM : std_logic;
+ SIGNAL CSUART : std_logic;
+ SIGNAL CSCTC : std_logic;
+ SIGNAL CSPIO : std_logic;
+
+BEGIN
+
+ uut: ADDRESS_DECODER PORT MAP(
+ MMU_IN => MMU_IN,
+ MMU_OUT => MMU_OUT,
+ IORQ => IORQ,
+ RD => RD,
+ CSROML => CSROML,
+ CSROMH => CSROMH,
+ CSRAM => CSRAM,
+ CSUART => CSUART,
+ CSCTC => CSCTC,
+ CSPIO => CSPIO
+ );
+
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+ wait; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/sw/cpld/ADDRESS_DECODER_tcl.ini b/sw/cpld/ADDRESS_DECODER_tcl.ini deleted file mode 100644 index fae7b5f..0000000 --- a/sw/cpld/ADDRESS_DECODER_tcl.ini +++ /dev/null @@ -1,5 +0,0 @@ -[Tcl] -Start = Yes; -Process = YES; -Append = YES; -TclFilename = ADDRESS_DECODER.tcl; diff --git a/sw/cpld/address_decoder.STY b/sw/cpld/address_decoder.STY new file mode 100755 index 0000000..e9ce747 --- /dev/null +++ b/sw/cpld/address_decoder.STY @@ -0,0 +1,2 @@ +[STRATEGY-LIST]
+Normal=True, 1506346678
diff --git a/sw/cpld/address_decoder.b2_ b/sw/cpld/address_decoder.b2_ new file mode 100755 index 0000000..432d996 --- /dev/null +++ b/sw/cpld/address_decoder.b2_ @@ -0,0 +1 @@ + -collapse all -pterms 16 -nfanlimit 32 -cluster 5 -reduce bypin choose -xorsyn
diff --git a/sw/cpld/address_decoder.bl2 b/sw/cpld/address_decoder.bl2 new file mode 100755 index 0000000..b5f7d35 --- /dev/null +++ b/sw/cpld/address_decoder.bl2 @@ -0,0 +1,142 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE address_decoder
+#$ PINS 28 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ \
+# IORQ MMU_IN_2_ RD MMU_IN_1_ CSROML MMU_IN_0_ CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART \
+# MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_11_ MMU_IN_10_ \
+# MMU_IN_9_ MMU_IN_8_
+#$ NODES 34 op_ge_un24_csromh op_lt_un11_csromh un12_csromhZ0 N_117 N_181 \
+# op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0 MMU_IN_i_0_7 MMU_IN_i_0_6 MMU_IN_i_0_5 \
+# MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 MMU_IN_c_3 \
+# MMU_IN_c_4 MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 MMU_IN_c_c_12 MMU_IN_c_c_13 \
+# MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c un12_csromh_i_c \
+# MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.model address_decoder
+.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF \
+MMU_IN_12_.BLIF MMU_IN_11_.BLIF MMU_IN_10_.BLIF MMU_IN_9_.BLIF MMU_IN_8_.BLIF \
+MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF MMU_IN_3_.BLIF \
+MMU_IN_2_.BLIF MMU_IN_1_.BLIF MMU_IN_0_.BLIF op_ge_un24_csromh.BLIF \
+op_lt_un11_csromh.BLIF un12_csromhZ0.BLIF N_117.BLIF N_181.BLIF \
+op_lt_un11_cspio.BLIF N_56.BLIF N_54.BLIF N_51.BLIF IORQ_iZ0.BLIF \
+MMU_IN_i_0_7.BLIF MMU_IN_i_0_6.BLIF MMU_IN_i_0_5.BLIF MMU_IN_i_0_3.BLIF \
+MMU_IN_i_0_2.BLIF MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF MMU_IN_c_2.BLIF \
+MMU_IN_c_3.BLIF MMU_IN_c_4.BLIF MMU_IN_c_5.BLIF MMU_IN_c_6.BLIF \
+MMU_IN_c_7.BLIF MMU_IN_c_c_12.BLIF MMU_IN_c_c_13.BLIF MMU_IN_c_c_14.BLIF \
+MMU_IN_c_c_15.BLIF IORQ_c.BLIF op_ge_un24_csromh_i_c.BLIF un12_csromh_i_c.BLIF \
+MMU_IN_i_c_15.BLIF N_181_i_0_c.BLIF GND.BLIF N_184.BLIF
+.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ \
+MMU_OUT_13_ MMU_OUT_12_ op_ge_un24_csromh op_lt_un11_csromh un12_csromhZ0 \
+N_117 N_181 op_lt_un11_cspio N_56 N_54 N_51 IORQ_iZ0 MMU_IN_i_0_7 MMU_IN_i_0_6 \
+MMU_IN_i_0_5 MMU_IN_i_0_3 MMU_IN_i_0_2 MMU_IN_i_0_14 MMU_IN_i_0_13 MMU_IN_c_2 \
+MMU_IN_c_3 MMU_IN_c_4 MMU_IN_c_5 MMU_IN_c_6 MMU_IN_c_7 MMU_IN_c_c_12 \
+MMU_IN_c_c_13 MMU_IN_c_c_14 MMU_IN_c_c_15 IORQ_c op_ge_un24_csromh_i_c \
+un12_csromh_i_c MMU_IN_i_c_15 N_181_i_0_c GND N_184
+.names MMU_IN_i_c_15.BLIF N_117.BLIF op_ge_un24_csromh
+11 1
+.names MMU_IN_i_c_15.BLIF MMU_IN_i_0_14.BLIF op_lt_un11_csromh
+11 1
+.names op_lt_un11_csromh.BLIF op_ge_un24_csromh_i_c.BLIF un12_csromhZ0
+11 1
+.names MMU_IN_i_0_14.BLIF MMU_IN_i_0_13.BLIF N_117
+11 1
+.names op_lt_un11_cspio.BLIF N_184.BLIF N_181
+11 1
+.names N_56.BLIF MMU_IN_i_0_7.BLIF op_lt_un11_cspio
+11 1
+.names N_54.BLIF MMU_IN_i_0_6.BLIF N_56
+11 1
+.names N_51.BLIF MMU_IN_i_0_5.BLIF N_54
+11 1
+.names MMU_IN_i_0_3.BLIF MMU_IN_i_0_2.BLIF N_51
+11 1
+.names IORQ_c.BLIF IORQ_iZ0
+0 1
+.names MMU_IN_c_7.BLIF MMU_IN_i_0_7
+0 1
+.names MMU_IN_c_6.BLIF MMU_IN_i_0_6
+0 1
+.names MMU_IN_c_5.BLIF MMU_IN_i_0_5
+0 1
+.names MMU_IN_c_3.BLIF MMU_IN_i_0_3
+0 1
+.names MMU_IN_c_2.BLIF MMU_IN_i_0_2
+0 1
+.names MMU_IN_c_c_14.BLIF MMU_IN_i_0_14
+0 1
+.names MMU_IN_c_c_13.BLIF MMU_IN_i_0_13
+0 1
+.names op_ge_un24_csromh.BLIF op_ge_un24_csromh_i_c
+0 1
+.names un12_csromhZ0.BLIF un12_csromh_i_c
+0 1
+.names MMU_IN_c_c_15.BLIF MMU_IN_i_c_15
+0 1
+.names N_181.BLIF N_181_i_0_c
+0 1
+.names GND
+.names MMU_IN_c_4.BLIF IORQ_iZ0.BLIF N_184
+11 1
+.names MMU_IN_c_c_15.BLIF MMU_OUT_15_
+1 1
+0 0
+.names op_ge_un24_csromh_i_c.BLIF CSROML
+1 1
+0 0
+.names un12_csromh_i_c.BLIF CSROMH
+1 1
+0 0
+.names MMU_IN_i_c_15.BLIF CSRAM
+1 1
+0 0
+.names GND.BLIF CSUART
+1 1
+0 0
+.names GND.BLIF CSCTC
+1 1
+0 0
+.names N_181_i_0_c.BLIF CSPIO
+1 1
+0 0
+.names MMU_IN_c_c_14.BLIF MMU_OUT_14_
+1 1
+0 0
+.names MMU_IN_c_c_13.BLIF MMU_OUT_13_
+1 1
+0 0
+.names MMU_IN_c_c_12.BLIF MMU_OUT_12_
+1 1
+0 0
+.names MMU_IN_2_.BLIF MMU_IN_c_2
+1 1
+0 0
+.names MMU_IN_3_.BLIF MMU_IN_c_3
+1 1
+0 0
+.names MMU_IN_4_.BLIF MMU_IN_c_4
+1 1
+0 0
+.names MMU_IN_5_.BLIF MMU_IN_c_5
+1 1
+0 0
+.names MMU_IN_6_.BLIF MMU_IN_c_6
+1 1
+0 0
+.names MMU_IN_7_.BLIF MMU_IN_c_7
+1 1
+0 0
+.names MMU_IN_12_.BLIF MMU_IN_c_c_12
+1 1
+0 0
+.names MMU_IN_13_.BLIF MMU_IN_c_c_13
+1 1
+0 0
+.names MMU_IN_14_.BLIF MMU_IN_c_c_14
+1 1
+0 0
+.names MMU_IN_15_.BLIF MMU_IN_c_c_15
+1 1
+0 0
+.names IORQ.BLIF IORQ_c
+1 1
+0 0
+.end
diff --git a/sw/cpld/address_decoder.bl3 b/sw/cpld/address_decoder.bl3 new file mode 100755 index 0000000..70065ad --- /dev/null +++ b/sw/cpld/address_decoder.bl3 @@ -0,0 +1,52 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE address_decoder
+#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ \
+# IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC \
+# CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
+.model address_decoder
+.inputs MMU_IN_15_.BLIF IORQ.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF \
+MMU_IN_12_.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \
+MMU_IN_3_.BLIF MMU_IN_2_.BLIF
+.outputs MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ \
+MMU_OUT_13_ MMU_OUT_12_
+.names MMU_IN_15_.BLIF MMU_OUT_15_
+1 1
+0 0
+.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROML
+-1- 1
+1-- 1
+--1 1
+000 0
+.names MMU_IN_15_.BLIF MMU_IN_14_.BLIF MMU_IN_13_.BLIF CSROMH
+--0 1
+-1- 1
+1-- 1
+001 0
+.names MMU_IN_15_.BLIF CSRAM
+0 1
+1 0
+.names CSUART
+ 0
+.names CSCTC
+ 0
+.names IORQ.BLIF MMU_IN_7_.BLIF MMU_IN_6_.BLIF MMU_IN_5_.BLIF MMU_IN_4_.BLIF \
+MMU_IN_3_.BLIF MMU_IN_2_.BLIF CSPIO
+-----1- 1
+----0-- 1
+---1--- 1
+--1---- 1
+-1----- 1
+1------ 1
+------1 1
+0000100 0
+.names MMU_IN_14_.BLIF MMU_OUT_14_
+1 1
+0 0
+.names MMU_IN_13_.BLIF MMU_OUT_13_
+1 1
+0 0
+.names MMU_IN_12_.BLIF MMU_OUT_12_
+1 1
+0 0
+.end
diff --git a/sw/cpld/address_decoder.d0 b/sw/cpld/address_decoder.d0 new file mode 100755 index 0000000..cb8545c --- /dev/null +++ b/sw/cpld/address_decoder.d0 @@ -0,0 +1 @@ + -dev mach4_DT_NCE -cluster 5
diff --git a/sw/cpld/address_decoder.data b/sw/cpld/address_decoder.data new file mode 100755 index 0000000..a01c4bd --- /dev/null +++ b/sw/cpld/address_decoder.data @@ -0,0 +1,240 @@ +MODELDATA
+MODELDATA_VERSION "1.0";
+DESIGN "address_decoder";
+DATE "Mon Nov 13 11:47:14 2017";
+VENDOR "Lattice Semiconductor Co. Ltd.";
+PROGRAM "STAMP Model Generator";
+
+/* port drive, max transition and max capacitance */
+PORTDATA
+MMU_IN_2: MAXTRANS(0.0);
+MMU_IN_3: MAXTRANS(0.0);
+MMU_IN_4: MAXTRANS(0.0);
+MMU_IN_5: MAXTRANS(0.0);
+MMU_IN_6: MAXTRANS(0.0);
+MMU_IN_7: MAXTRANS(0.0);
+MMU_IN_8: MAXTRANS(0.0);
+MMU_IN_9: MAXTRANS(0.0);
+MMU_IN_10: MAXTRANS(0.0);
+MMU_IN_11: MAXTRANS(0.0);
+MMU_IN_12: MAXTRANS(0.0);
+MMU_IN_13: MAXTRANS(0.0);
+MMU_IN_14: MAXTRANS(0.0);
+MMU_IN_15: MAXTRANS(0.0);
+CSCTC: MAXTRANS(0.0);
+CSPIO: MAXTRANS(0.0);
+CSRAM: MAXTRANS(0.0);
+CSROMH: MAXTRANS(0.0);
+CSROML: MAXTRANS(0.0);
+CSUART: MAXTRANS(0.0);
+MMU_OUT_12: MAXTRANS(0.0);
+MMU_OUT_13: MAXTRANS(0.0);
+MMU_OUT_14: MAXTRANS(0.0);
+MMU_OUT_15: MAXTRANS(0.0);
+ENDPORTDATA
+
+/* timing arc data */
+TIMINGDATA
+
+ARCDATA
+MMU_IN_2_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_3_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_4_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_5_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_6_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_7_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_8_CSCTC_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_8_CSPIO_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_8_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_9_CSCTC_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_9_CSPIO_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_9_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_10_CSCTC_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_10_CSPIO_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_10_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_11_CSCTC_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_11_CSPIO_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_11_CSUART_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_12_CSCTC_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ARCDATA
+MMU_IN_12_CSPIO_delay:
+CELL_RISE(scalar) {
+VALUES(15.0);
+}
+CELL_FALL(scalar) {
+VALUES(15.0);
+}
+ENDARCDATA
+
+ENDTIMINGDATA
+ENDMODELDATA
diff --git a/sw/cpld/address_decoder.edi b/sw/cpld/address_decoder.edi new file mode 100755 index 0000000..d0d8378 --- /dev/null +++ b/sw/cpld/address_decoder.edi @@ -0,0 +1,367 @@ +@Eq6wVJKxL#xTixT#_x2#aLiL
+q6wVVK lbD7wLLpFtL
+p6LVLKqkwVV1[tL
+p6L.LfVb G vq6B.LfVb k Vq1[LVtp
+t6LDLddyvLDL
+6LfLd dw
+VL7LLLLdLw6TMdVBvLMsFmpsLLsLFsn5sQL5LtnL
+LLLL6Ldv9yLb" 7TB e1ww,dL eCN7
+"LtLLLLBL 6 bvO"MTLB 17 w"K[LV6w bD"75LNNpnt"
+tLLLL
+LLttL
+L6LVLVH d17LveM9vLsL
+6LVLKqkwVV1[tL
+pLLLLV6edb917 bLOy6M7 hxVwV7Kwwbdt7tLL
+LLeLV6L1J1F8LxV61e 1BgzV#Li8C#
+2LtLLLL6L[LfwLVwBM [Lw6gV fLB8Vk#CgtT
+gLLLLLLLLwL76 dKVVv
+eLLLLLLLLLL6L BdbLL6a qVwwebda7ULUggj
+tLtLLLLLLLL6LBLdbL LC6p qVwwebdC78LgjtULtL
+LLLLLLLLBLb6L Cd6sqLVwe bd7w8LjCtUtgL
+LLLLLLtL
+LLLLLLLtLL
+LL
+LLtLL6L1e1VSLUC6ueL1Vg1V LB8z##2itCL
+LLLLLLw6V[Bf LLw6MV[fwBgV #Lg8TkgCLtL
+LLLLLL6LdwV7v eKLVL
+LLLLLLLLBLb6L adqLw6e dV7wLbgajUtUtgL
+LLLLLLLLLLb6 BCdpLqLw6e dV7wLbjCU8tg
+tLLLLLLLL
+LLtLLLLtL
+LLLLLLtL
+6LeL1VL1lCL8V61e 1BgzV#Li8C#
+2LtLLLL6L[LfwLVwBM [Lw6gV fLB8Vk#CgtT
+gLLLLLLLLwL76 dKVVv
+eLLLLLLLLLL6L BdbLL6a qVwwebda7ULUggj
+tLtLLLLLLLL6LBLdbL LC6p qVwwebdC78LgjtULtL
+LLLLLLtLL
+LLLLLLLtL
+tL
+LLLLLV61ea1SLLU6u1e1VBgV #L8zC#2iLtL
+LLLL[Lw6LVBfM Lww6V[ fBg8V#LCgTk
+gLtLLLLLLLL76dwKVv
+eLVLLLLLLLL6LBLdbL 6aqLVwe bd7wULgagjtULtL
+LLLLLLLLBLb6L Cd6pqLVwe bd7w8LjCtUtgL
+LLLLLLtL
+LLLLLLLtLL
+LL
+LLt
+LLt1Lw6vh f bL
+ L.LL6LwVKq[kVVp1tLL
+LLdLV67eb9O1 b7Ly6VM hKxwVd7wwLbt7LtL
+6LeL1VL1xJixT#_T2xa#ixL#V61e 1BgzV#Li8C#
+2LtLLLL6L[LfwLV9hvVb[ wLv61V[fwBgV #Lg8TkgCLtL
+LLLLLL6LdwV7v eKLVL
+LLLLLLLLBLb6L 6d vv 6 LvVM7GVGLCU8_GLG"CU8_56:s"ptt(LtsqLw6e dV7wLbjCU8tg
+tLLLLLLLLLL6L BdbvL 6 LvV67 VvLMUG_GgaLUG"UGU_ga56:sts"FQttLqLw6e dV7wLbgajUtUtgL
+LLLLLLLLLLb6 BCdaLLi6] qVwwebdC78LgjtULtL
+LLLLLLLLBLb6L id6xqLVwe bd7w8LjCtUtgL
+LLLLLLLLLLb6 B2dTLGikaqLw6e dV7wLbgajUtUtgL
+LLLLLLLLLLb6 B2dTLGi)aqLw6e dV7wLbgajUtUtgL
+LLLLLLLLLLb6 B2dTLGiLJw6 qdVweLba7jUUgtg
+tLLLLLLLLLL6L BdbTLU2gJLiw6 qdVweLba7jUUgtg
+tLLLLLLLLLL6L BdbTL22Lg62 qVwwebda7ULUggj
+tLtLLLLLLLL6LBLdbL j2CT6aqLVwe bd7wULgagjtULtL
+LLLLLLtLL
+LLLLLL6LeLdbV7D7
+dLLLLLLLL6LwLd7vDV7LeUG_GZCp8FZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp8nZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp8QZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp85ZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp8(ZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp8mZL_w6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GZCp8sZF_[Lw6iVVfBK LLw6M1e1VKiLVUCuS1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7GLUG8_ZC_psZ6n[LfwiVLVBKM LwV61eV1KiSLUC6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLCU8_ZZ_pLs6QV[fwKiLVwBM eLV6i1V1CKSLLU6uh1 w vi LVMK9vsettLtLLLLLLLL
+LLtLLLLLLLLwL76vD7dLeGV_GCUp8ZZ5_Lsw6V[VfKi LwB6MeL1Vi1LVCKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GgaZU_psZ6F[LfwiVLVBKM LwV61eV1KiSLUa6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLaUU_pgZZn_Lsw6V[VfKi LwB6MeL1Vi1LVaKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_GgaZU_psZ6Q[LfwiVLVBKM LwV61eV1KiSLUa6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLaUU_pgZZ5_Lsw6V[VfKi LwB6MeL1Vi1LVaKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeiC]aLZ6pV[fwKiLVwBM eLV6i1V1CKSLLU6uh1 w vi LVMK9vsettLtLLLLLLLL
+LLtLLLLLLLLwL76vD7dLe2VaTGipkLZw6V[VfKi LwB6MeL1Vi1LVaKuSLUw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7Lei2aTZGp)[Lw6iVVfBK LLw6M1e1VKiLVUauS1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7TLi2ZJpG[Lw6iVVfBK LLw6M1e1VKiLVUauS1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7TLU2gJZi6p[LfwiVLVBKM LwV61eV1KiSLUa6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7dev2VTL22Zg6p[LfwiVLVBKM LwV61eV1KiSLUa6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7dev2VTLajZC6p[LfwiVLVBKM LwV61eV1KiSLUa6u1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devyV7L_Fe(wDbB[Lw6iVVfBK LLw6M1e1VKiLVxJF81Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV77LFye(D_bB_wszP_6Q[LfwiVLVBKM LwV61eV1Ki8LxJ6F1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLCU8___(w[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_G_Cw8L_65V[fwKiLVwBM eLV6i1V1CK8L6l1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLCU8___nw[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeUG_G_Cw8L_6FV[fwKiLVwBM eLV6i1V1CK8L6l1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLCU8___sw6Q[LfwiVLVBKM LwV61eV1Ki8LlC1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7GLUG8__Cswn_[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LesyF7D_ e9bLMw6V[VfKi LwB6MeL1Vi1LVJKF8Lxw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7Leszs_6([LfwiVLVBKM LwV61eV1Ki8LxJ6F1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devzV_LPsLsw6V[VfKi LwB6MeL1Vi1LVJKF8Lxw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7Leszm_6o[LfwiVLVBKM LwV61eV1Ki8LxJ6F1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devzV_LLQ6oV[fwKiLVwBM eLV6i1V1JK8LLx6Fh1 w vi LVMK9vsettLtLLLLLLLL
+LLtLLLLLLLLwL76vD7dLezVn_L5w6V[VfKi LwB6MeL1Vi1LVJKF8Lxw6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7Le5z5_[Lw6iVVfBK LLw6M1e1VKiLVxJF81Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7_L5z6m[LfwiVLVBKM LwV61eV1Ki8LxJ6F1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7dev8V_Lss_P6w[LfwiVLVBKM LwV61eV1Ki8LlC1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7GLUG8__Csw5_[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LesyF7D_ e9b_M6w[LfwiVLVBKM LwV61eV1Ki8LlC1Lw6vh V KivLeMt9tsLtLLLLLLLLtLL
+LLLLLLLL6LDwd7evV7BL_b_OyVQ7_F ebD_Mw9[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6LwLd7vDV7LeiC]aL_6wV[fwKiLVwBM eLV6i1V1CK8L6l1L wvhi V MKvLset9LtLtLLLLLLLLLtL
+LLLLLLLL76Dw7devGVGLCU8___mw[Lw6iVVfBK LLw6M1e1VKiLVlCL8w6h1 vKiLVeM9vtsttLLLLLLLLtL
+LLLLLLLLL6L7LLVbdOBV_7_FyeQD_M 9bALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVszs_tP
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLV_bOByV7__FeQbDM w9t_LtL
+LLLLLLLL
+tLtLLLLLLLL7LV6bdBLd__1sys7D_ e9bLMb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVzKm_os
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVyKF7_s ebDtMt9L
+LLLLLLLLtLLtL
+LLLLLLLLV6d77LsyeFD_M 9bLZ6pwA7b
+VLqLLLLLLLL6LBLdbi LVaKwL76vD7dieVVyK7L_seFbDM t9
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLVsyF7D_ e9b_Mtw
+tLLLLLLLLtLtLL
+LLLLLLLL6Ld7LVs8s_6mAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKi_Lsztst(L
+LLLLLLLLLLb6 BVdKisLLC76Dw7devVVKi_LsztstPL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7_Ls8LP6swA7b
+VLqLLLLLLLL6LBLdbi LVaKwL76vD7dieVVyK7L_Fe(wDbB
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLV8KP_sst_twL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7BL_b_1yds7_sBewD6bAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKi_L5ztm
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLVFy(7D_BetwtbL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7_L586(AL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKi_L5zt5
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLV5zm_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLV8dQ_L5b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVzKn_t5LtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVzK_Lt5t5L
+LLLLLLLLtLLtL
+LLLLLLLLV6d7_L586sAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKi_LQzto
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLV5zn_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVCd]a_ipwLZb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVCK]a_itw
+tLLLLLLLLLL6L BdbKiLVLC6sDwd7evV7KiLVFy(7D_Be_wzbP_Qs
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__mpL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__tm
+tLLLLLLLLLL6L BdbKiLVLC6sDwd7evV7KiLV5zm_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__(pL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__t(
+tLLLLLLLLLL6L BdbKiLVLC6sDwd7evV7KiLV5z5_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__5pL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__t5
+tLLLLLLLLLL6L BdbKiLVLC6sDwd7evV7KiLV5zn_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__npL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__tn
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLVQzo_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__FpL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__tF
+tLLLLLLLLLL6L BdbKiLVLC6sDwd7evV7KiLVQzo_
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUw8__spQ_ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVUG_G_Cw8Q_tsLtL
+LLLLLLLLBLb6i VdCKsLwL76vD7dieVVzK_LostmLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVzK_L(stsLtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8___pwn_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__tstnL
+LLLLLLLLLLb6 BVdKisLLC76Dw7devVVKi_Lsztst(L
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__C6pAL7bVwLqL
+LLLLLLLLBLb6i Vd6KMLhVVMG GLCU8_5LtsLtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8_L_6swA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUs8QL
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__6FAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKiGLUG8_ZC_pFZ
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUw8__tF
+tLLLLLLLLtLtLL
+LLLLLLLL6Ld7LVUG_G_CF8ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiMLV6VM hGLUG8_LCtstnL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUG8_ZC_pFZ
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__6nAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKiGLUG8_ZC_pnZ
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUw8__tn
+tLLLLLLLLtLtLL
+LLLLLLLL6Ld7LVUG_G_Cn8ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiMLV6VM hGLUG8_LCtstFL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUG8_ZC_pnZ
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__6QAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKiGLUG8_ZC_pQZ
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVyK(7_FBewDzb__QstPLtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8_L_6QwA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUs8sL
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUp8ZZt_tQL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__C5eL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUp8ZZt_t5L
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUG8__C5wt_LtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8_L_65wA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUs8pL
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUp8ZZt_t5L
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__C(eL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUp8ZZt_t(L
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUG8__C(wt_LtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8_L_6(wA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUo8tLLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVGKGLCU8_ZZ_pt(
+tLLLLLLLLtLtLL
+LLLLLLLL6Ld7LVUG_G_Ce8L_6mwA7b
+VLqLLLLLLLL6LBLdbi LVaKwL76vD7dieVVGKGLCU8_ZZ_ptm
+tLLLLLLLLLL6L BdbKiLVLC6pDwd7evV7KiLVUG_G_Cw8t_tmL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__C6mAL7bVwLqL
+LLLLLLLLBLb6i Vd6KMLhVVMG GLCU8_tLtPL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUG8_ZC_pmZ
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUP8L_b6wAq7
+VLLLLLLLLLL6L BdbKiLVV6MM hLVUG_GLCm8
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUo8L_b6wAq7
+VLLLLLLLLLL6L BdbKiLVV6MM hLVUG_GLC(8
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUs8p_ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiMLV6VM hGLUG8_LCt5
+tLLLLLLLLtLtLL
+LLLLLLLL6Ld7LVUG_G_Cs86sAL7bVwLqL
+LLLLLLLLBLb6i Vd6KMLhVVMG GLCU8_tLtQL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__CLs6FwA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUn8tLLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVGKGLCU8_ZZ_ptstFL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__CLs6nwA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUF8tLLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVGKGLCU8_ZZ_ptstnL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__CLs6QwA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUs8tLLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVGKGLCU8_ZZ_ptstQL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__CLs65wA7b
+VLqLLLLLLLL6LBLdbi LV6KMMhVLVG _GCUp8tLLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVGKGLCU8_ZZ_ptst5L
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUG8__Cee__Ls6FwA7b
+VLqLLLLLLLL6LBLdbi LVaKwL76vD7dieVVGKGLCU8_ZZ_ptstFL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUGU_gaZZ_ptstFL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUGU_gaF_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GaUZUpgsZF_
+tLtLLLLLLLL6LBLdbi LV6KMMhVLVG _GaULUng
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__sen_ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVUG_GZCp8sZn_
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUw8__tstnL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUGU_gaZZ_ptstnL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUGU_gan_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GaUZUpgsZn_
+tLtLLLLLLLL6LBLdbi LV6KMMhVLVG _GaULUFg
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__seQ_ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVUG_GZCp8sZQ_
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUw8__tstQL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUGU_gaZZ_ptstQL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUGU_gaQ_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GaUZUpgsZQ_
+tLtLLLLLLLL6LBLdbi LV6KMMhVLVG _GaULUsg
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVGd_GCUe8__se5_ALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVUG_GZCp8sZ5_
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLVGK_GCUw8__tst5L
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiGLUGU_gaZZ_ptst5L
+LLLLLLLLtLLtL
+LLLLLLLLV6d7GLUGU_ga5_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GaUZUpgsZ5_
+tLtLLLLLLLL6LBLdbi LV6KMMhVLVG _GaULUpg
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVCd]a_i6eAL7bVwLqL
+LLLLLLLLBLb6i VdaKLL76Dw7devVVKiaLiCp]tZLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVCKaL_iw]
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVCd]aLib6wAq7
+VLLLLLLLLLL6L BdbKiLViC]aLtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVVCKaLZip]
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVid6xAL7bVwLqL
+LLLLLLLLBLb6i VdiKxLLtL
+LLLLLLLL
+tLtLLLLLLLL7LV6bdBLV__OFyQ7D_ e9b_MewL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVbKOBV_7_FyeQD_M 9bt_twL
+LLLLLLLLLLb6 BVdKisLLC76Dw7devVVKi7LsyeFD_M 9b
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLV2KaTGipktZLtL
+LLLLLLLL
+tLtLLLLLLLL7LV62dTLGikaALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVi2aTZGpk
+tLtLLLLLLLL6LBLdbi LV2KaTGi
+kLtLLLLLLLLtL
+tLLLLLLLL6L7LLVydF7_s ebD_Mw9L_6ewA7b
+VLqLLLLLLLL6LBLdbi LVaKwL76vD7dieVVyK7L_seFbDM w9t_LtL
+LLLLLLLLBLb6i VdCKpLwL76vD7dieVV2KTLGi)atZtpL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7TLi2)aLGb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLV2KaTGip)tZLtL
+LLLLLLLLBLb6i Vd2KTLGi)aLtL
+LLLLLLLL
+tLtLLLLLLLL7LV6GdGLCU8___ew5_Lsb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVGK_GCUw8__tst5L
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKi_LsztmtoL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKi_LsztstPL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiTLi2ZJpG
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLV2dJTGiALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVi2JTpGtZLtL
+LLLLLLLLBLb6i Vd2KTLGitJL
+LLLLLLLLtLLtL
+LLLLLLLLV6d7TLU2gJLib6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLV2KJTiUpgtZLtL
+LLLLLLLLBLb6i Vd2KTLiUgJLtL
+LLLLLLLL
+tLtLLLLLLLL7LV62dTL22Lgb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLV2KgT22tZtpL
+LLLLLLLLLLb6 BVdKiTL22tg
+2LLLLLLLLtLtLL
+LLLLLLLL6Ld7LVs8P_ws__epL_b6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLV8KP_sst_twL
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiTLj2ZCpa
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLV2dCTajALb6Vwq7L
+LLLLLLLLLLb6 BVdKiLL6aDwd7evV7KiLVj2CTpatZLtL
+LLLLLLLLBLb6i Vd2KTLajtCL
+LLLLLLLLtLLtL
+LLLLLLLLV6d78LxzALb6Vwq7L
+LLLLLLLLLLb6 BVdKipLLC76Dw7devVVKiTL22Zgp2
+tLtLLLLLLLL6LBLdbi LVCK6pwLd7vDV7ieLV2KJTiUpgtZLtL
+LLLLLLLL
+tLtLLLLLLLL7LV68d_LQsLPb6wAq7
+VLLLLLLLLLL6L BdbKiLV6awLd7vDV7ieLVyK(7_FBewDzb__QstPLtL
+LLLLLLLLBLb6i VdCKsLwL76vD7dieVVyK7L_Fe(wDbB
+tLtLLLLLLLLtL
+tLLLLLLLL6L7LLVldL262wA7b
+VLqLLLLLLLLtL
+tLLLLLLLL
+LLtLLLLtL
+LLLLLLtL
+LtL
+V6Dq7wLOxJixT#_T2xa#ixL#V61eV1KixLxJTiT##_2x#aix1Lw6vh V KibL ft.tt
+
+
+t
\ No newline at end of file diff --git a/sw/cpld/address_decoder.eq3 b/sw/cpld/address_decoder.eq3 new file mode 100755 index 0000000..8eb8577 --- /dev/null +++ b/sw/cpld/address_decoder.eq3 @@ -0,0 +1,49 @@ + ispDesignEXPERT 8.3.02.12
+
+Design address_decoder created Thu Nov 23 11:54:43 2017
+
+
+ P-Terms Fan-in Fan-out Type Name (attributes)
+--------- ------ ------- ---- -----------------
+ 1 1 1 Pin MMU_OUT_15_
+ 1 3 1 Pin CSROML-
+ 1 3 1 Pin CSROMH-
+ 1 1 1 Pin MMU_OUT_14_
+ 1 1 1 Pin CSRAM
+ 1 1 1 Pin MMU_OUT_13_
+ 0 0 1 Pin CSUART
+ 1 1 1 Pin MMU_OUT_12_
+ 0 0 1 Pin CSCTC
+ 1 7 1 Pin CSPIO-
+=========
+ 8 P-Term Total: 8
+ Total Pins: 21
+ Total Nodes: 0
+ Average P-Term/Output: 0
+
+
+Equations:
+
+MMU_OUT_15_ = (MMU_IN_15_);
+
+!CSROML = (!MMU_IN_15_ & !MMU_IN_14_ & !MMU_IN_13_);
+
+!CSROMH = (!MMU_IN_15_ & !MMU_IN_14_ & MMU_IN_13_);
+
+MMU_OUT_14_ = (MMU_IN_14_);
+
+CSRAM = (!MMU_IN_15_);
+
+MMU_OUT_13_ = (MMU_IN_13_);
+
+CSUART = (0);
+
+MMU_OUT_12_ = (MMU_IN_12_);
+
+CSCTC = (0);
+
+!CSPIO = (!IORQ & !MMU_IN_7_ & !MMU_IN_6_ & !MMU_IN_5_ & MMU_IN_4_ & !MMU_IN_3_ & !MMU_IN_2_);
+
+
+Reverse-Polarity Equations:
+
diff --git a/sw/cpld/address_decoder.fti b/sw/cpld/address_decoder.fti new file mode 100755 index 0000000..b762b12 --- /dev/null +++ b/sw/cpld/address_decoder.fti @@ -0,0 +1,90 @@ +#PLAFILE address_decoder.tt4
+#DATE 09/25/2017
+#DESIGN <no design name>
+#DEVICE mach432
+
+DATA LOCATION CSCTC:B_12_28 // OUT
+DATA LOCATION CSPIO:B_8_29 // OUT
+DATA LOCATION CSRAM:B_13_26 // OUT
+DATA LOCATION CSROMH:B_10_25 // OUT
+DATA LOCATION CSROML:B_14_24 // OUT
+DATA LOCATION CSUART:B_9_27 // OUT
+DATA LOCATION IORQ:B_*_30 // INP
+DATA LOCATION MMU_IN_12_:A_*_18 // INP
+DATA LOCATION MMU_IN_13_:A_*_19 // INP
+DATA LOCATION MMU_IN_14_:A_*_20 // INP
+DATA LOCATION MMU_IN_15_:A_*_21 // INP
+DATA LOCATION MMU_IN_2_:A_*_7 // INP
+DATA LOCATION MMU_IN_3_:A_*_6 // INP
+DATA LOCATION MMU_IN_4_:A_*_5 // INP
+DATA LOCATION MMU_IN_5_:A_*_4 // INP
+DATA LOCATION MMU_IN_6_:A_*_3 // INP
+DATA LOCATION MMU_IN_7_:A_*_2 // INP
+DATA LOCATION MMU_OUT_12_:B_0_39 // OUT
+DATA LOCATION MMU_OUT_13_:B_4_38 // OUT
+DATA LOCATION MMU_OUT_14_:B_1_37 // OUT
+DATA LOCATION MMU_OUT_15_:B_5_36 // OUT
+DATA IO_DIR CSCTC:OUT
+DATA IO_DIR CSPIO:OUT
+DATA IO_DIR CSRAM:OUT
+DATA IO_DIR CSROMH:OUT
+DATA IO_DIR CSROML:OUT
+DATA IO_DIR CSUART:OUT
+DATA IO_DIR IORQ:IN
+DATA IO_DIR MMU_IN_12_:IN
+DATA IO_DIR MMU_IN_13_:IN
+DATA IO_DIR MMU_IN_14_:IN
+DATA IO_DIR MMU_IN_15_:IN
+DATA IO_DIR MMU_IN_2_:IN
+DATA IO_DIR MMU_IN_3_:IN
+DATA IO_DIR MMU_IN_4_:IN
+DATA IO_DIR MMU_IN_5_:IN
+DATA IO_DIR MMU_IN_6_:IN
+DATA IO_DIR MMU_IN_7_:IN
+DATA IO_DIR MMU_OUT_12_:OUT
+DATA IO_DIR MMU_OUT_13_:OUT
+DATA IO_DIR MMU_OUT_14_:OUT
+DATA IO_DIR MMU_OUT_15_:OUT
+DATA PW_LEVEL MMU_IN_7_:0
+DATA SLEW MMU_IN_7_:0
+DATA PW_LEVEL MMU_IN_6_:0
+DATA SLEW MMU_IN_6_:0
+DATA PW_LEVEL MMU_IN_15_:0
+DATA SLEW MMU_IN_15_:0
+DATA PW_LEVEL MMU_IN_5_:0
+DATA SLEW MMU_IN_5_:0
+DATA PW_LEVEL MMU_IN_4_:0
+DATA SLEW MMU_IN_4_:0
+DATA PW_LEVEL MMU_OUT_15_:0
+DATA SLEW MMU_OUT_15_:0
+DATA PW_LEVEL MMU_IN_3_:0
+DATA SLEW MMU_IN_3_:0
+DATA PW_LEVEL IORQ:0
+DATA SLEW IORQ:0
+DATA PW_LEVEL MMU_IN_2_:0
+DATA SLEW MMU_IN_2_:0
+DATA PW_LEVEL CSROML:0
+DATA SLEW CSROML:0
+DATA PW_LEVEL CSROMH:0
+DATA SLEW CSROMH:0
+DATA PW_LEVEL MMU_OUT_14_:0
+DATA SLEW MMU_OUT_14_:0
+DATA PW_LEVEL CSRAM:0
+DATA SLEW CSRAM:0
+DATA PW_LEVEL MMU_OUT_13_:0
+DATA SLEW MMU_OUT_13_:0
+DATA PW_LEVEL CSUART:0
+DATA SLEW CSUART:0
+DATA PW_LEVEL MMU_OUT_12_:0
+DATA SLEW MMU_OUT_12_:0
+DATA PW_LEVEL CSCTC:0
+DATA SLEW CSCTC:0
+DATA PW_LEVEL CSPIO:0
+DATA SLEW CSPIO:0
+DATA PW_LEVEL MMU_IN_14_:0
+DATA SLEW MMU_IN_14_:0
+DATA PW_LEVEL MMU_IN_13_:0
+DATA SLEW MMU_IN_13_:0
+DATA PW_LEVEL MMU_IN_12_:0
+DATA SLEW MMU_IN_12_:0
+END
diff --git a/sw/cpld/address_decoder.grp b/sw/cpld/address_decoder.grp new file mode 100755 index 0000000..eb72f1f --- /dev/null +++ b/sw/cpld/address_decoder.grp @@ -0,0 +1,3 @@ +
+GROUP MACH_SEG_B CSPIO CSROML CSROMH MMU_OUT_12_ MMU_OUT_14_ MMU_OUT_13_
+ CSRAM MMU_OUT_15_ CSUART CSCTC
\ No newline at end of file diff --git a/sw/cpld/address_decoder.jed b/sw/cpld/address_decoder.jed new file mode 100755 index 0000000..dcf247b --- /dev/null +++ b/sw/cpld/address_decoder.jed @@ -0,0 +1,288 @@ +|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+TITLE:
+AUTHOR:
+PATTERN:
+COMPANY:
+REVISION:
+DATE: Thu Nov 23 11:55:45 2017
+
+ABEL mach432
+ *
+QP44*
+QF16160*
+G0*F0*
+NOTE Part Number : M4-32/32-15JC *
+NOTE Handling of Preplacements No Change *
+NOTE Use placement data from address_decoder.vct *
+NOTE Global clocks routable as PT clocks? N *
+NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y *
+NOTE SET/RESET treated as DONT_CARE? N *
+NOTE Reduce Unforced Global Clocks? N *
+NOTE Iterate between partitioning and place/route? Y *
+NOTE Balanced partitioning? Y *
+NOTE Reduce Routes Per Placement? N *
+NOTE Spread Placement? Y *
+NOTE Run Time Upper Bound in 15 minutes 0 *
+NOTE Table of pin names and numbers*
+NOTE PINS MMU_IN_7_:2 MMU_IN_6_:3 MMU_IN_15_:21 MMU_IN_5_:4*
+NOTE PINS MMU_IN_4_:5 MMU_OUT_15_:36:66 MMU_IN_3_:6 IORQ:30*
+NOTE PINS MMU_IN_2_:7 CSROML:24:75 CSROMH:25:71 MMU_OUT_14_:37:62*
+NOTE PINS CSRAM:26:74 MMU_OUT_13_:38:65 CSUART:27:70 MMU_OUT_12_:39:61*
+NOTE PINS CSCTC:28:73 CSPIO:29:69 MMU_IN_14_:20 MMU_IN_13_:19*
+NOTE PINS MMU_IN_12_:18 *
+NOTE Table of node names and numbers*
+NOTE Interleaved Central Switch Matrices for BLOCKS 0 and 1 *
+L000000
+ 101111111111101110111111111111101111111111111111111111111111111111 11101110101011
+ 111011111111111011101011101111111111111111111111111111111111111111 11111111111111
+ 111111111111111111111111111111111111101111111111111111111111111111 11111111111111
+ 111111111111111111111111111011111111111111111111111111111111111111 11111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111 11101110101011*
+NOTE Non-CSM fuses for BLOCK 0 *
+L000480
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L000560 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L000640 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L000720 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L000800 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L000880 111111111111111111111111111111111111111111111111111111111111111111 11010011111110*
+L000960
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L001040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001120 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001200 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001280 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001360 111111111111111111111111111111111111111111111111111111111111111111 11111011111110*
+L001440
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L001520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001600 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001680 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001760 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L001840 111111111111111111111111111111111111111111111111111111111111111111 11110111111110*
+L001920
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L002000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002080 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002160 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002240 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002320 111111111111111111111111111111111111111111111111111111111111111111 11111111111110*
+L002400
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L002480 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002560 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002640 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002720 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L002800 111111111111111111111111111111111111111111111111111111111111111111 11110011111110*
+L002880
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L002960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003120 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003200 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003280 111111111111111111111111111111111111111111111111111111111111111111 11111011111110*
+L003360
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L003440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003600 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003680 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L003760 111111111111111111111111111111111111111111111111111111111111111111 11110111111110*
+L003840
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L003920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004080 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004160 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004240 111111111111111111111111111111111111111111111111111111111111111111 11111111111110*
+L004320
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L004400 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004480 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004560 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004640 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004720 111111111111111111111111111111111111111111111111111111111111111111 11110011111110*
+L004800
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L004880 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L004960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005120 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005200 111111111111111111111111111111111111111111111111111111111111111111 11111011111110*
+L005280
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L005360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005600 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005680 111111111111111111111111111111111111111111111111111111111111111111 11110111111110*
+L005760
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L005840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L005920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006080 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006160 111111111111111111111111111111111111111111111111111111111111111111 11111111111110*
+L006240
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L006320 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006400 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006480 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006560 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006640 111111111111111111111111111111111111111111111111111111111111111111 11110011111110*
+L006720
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L006800 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006880 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L006960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007120 111111111111111111111111111111111111111111111111111111111111111111 11111011111110*
+L007200
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L007280 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007600 111111111111111111111111111111111111111111111111111111111111111111 11110111111110*
+L007680
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L007760 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L007920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L008000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L008080 111111111111111111111111111111111111111111111111111111111111111111 11111111111110*
+L008160
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+NOTE Non-CSM fuses for BLOCK 1 *
+L008320
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L008400 111111111111111111110111111111111111111111111111111111111111111111 11111111111111*
+L008480 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L008560 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L008640 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L008720 000000000000000000000000000000000000000000000000000000000000000000 00100011111010*
+L008800
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L008880 111111111111111111111111111111011111111111111111111111111111111111 11111111111111*
+L008960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009120 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009200 111111111111111111111111111111111111111111111111111111111111111111 00011011110000*
+L009280
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009600 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009680 111111111111111111111111111111111111111111111111111111111111111111 11010111110100*
+L009760
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L009920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010080 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010160 111111111111111111111111111111111111111111111111111111111111111111 11111111111010*
+L010240
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L010320 111111111111111111111111011111111111111111111111111111111111111111 11111111111111*
+L010400 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010480 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010560 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010640 111111111111111111111111111111111111111111111111111111111111111111 00110011111110*
+L010720
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L010800 111111111111111101111111111111111111111111111111111111111111111111 11111111111111*
+L010880 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L010960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011040 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011120 111111111111111111111111111111111111111111111111111111111111111111 00001011111000*
+L011200
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L011280 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011520 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011600 111111111111111111111111111111111111111111111111111111111111111111 11010111110010*
+L011680
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L011760 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L011920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012000 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012080 111111111111111111111111111111111111111111111111111111111111111111 11111111110000*
+L012160
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L012240 100111111111101011101111111011111111101111111111111111111111111111 11111111111111*
+L012320 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012400 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012480 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012560 111111111111111111111111111111111111111111111111111111111111111111 01110011111110*
+L012640
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L012720 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L012800 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012880 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L012960 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013040 111111111111111111111111111111111111111111111111111111111111111111 00001011110100*
+L013120
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013200 111111111111111110111111011111101111111111111111111111111111111111 11111111111111*
+L013280 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013440 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013520 111111111111111111111111111111111111111111111111111111111111111111 01010111110110*
+L013600
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013680 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013760 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L013920 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014000 111111111111111111111111111111111111111111111111111111111111111111 11101111111000*
+L014080
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014160 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+L014240 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014320 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014400 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014480 111111111111111111111111111111111111111111111111111111111111111111 00110011111010*
+L014560
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014640 111111111111111110111111111111111111111111111111111111111111111111 11111111111111*
+L014720 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014800 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014880 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L014960 111111111111111111111111111111111111111111111111111111111111111111 00001011110000*
+L015040
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015120 111111111111111110111111101111101111111111111111111111111111111111 11111111111111*
+L015200 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015280 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015360 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015440 111111111111111111111111111111111111111111111111111111111111111111 01010111110010*
+L015520
+ 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015600 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015680 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015760 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015840 111111111111111111111111111111111111111111111111111111111111111111 11111111111111*
+L015920 111111111111111111111111111111111111111111111111111111111111111111 11101111111110*
+L016000
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111
+ 000000000000000000000000000000000000000000000000000000000000000000 11111111111111*
+E
+0
+0000000000000000
+0
+0000000000000000
+*
+CB749*
+U00000000000000000000000000000000*
+0EAE
diff --git a/sw/cpld/address_decoder.jhd b/sw/cpld/address_decoder.jhd index 19ef983..f17745e 100644..100755 --- a/sw/cpld/address_decoder.jhd +++ b/sw/cpld/address_decoder.jhd @@ -1,3 +1,3 @@ - - -MODULE ADDRESS_DECODER +
+
+MODULE ADDRESS_DECODER
diff --git a/sw/cpld/address_decoder.jid b/sw/cpld/address_decoder.jid index f0d5286..2de560b 100644..100755 --- a/sw/cpld/address_decoder.jid +++ b/sw/cpld/address_decoder.jid @@ -1 +1 @@ -. ADDRESS_DECODER address_decoder.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld\address_decoder.vhd +. ADDRESS_DECODER address_decoder.vhd c:\_prossn\cpld.nao\address_decoder.vhd
diff --git a/sw/cpld/address_decoder.l0 b/sw/cpld/address_decoder.l0 new file mode 100755 index 0000000..9624ee4 --- /dev/null +++ b/sw/cpld/address_decoder.l0 @@ -0,0 +1 @@ + -ck Min -ce On -ar On -ap On -oe On -split 16 -cluster 5 -xor on -speed -ifb yes -sr no
diff --git a/sw/cpld/address_decoder.log b/sw/cpld/address_decoder.log new file mode 100755 index 0000000..cd0a45f --- /dev/null +++ b/sw/cpld/address_decoder.log @@ -0,0 +1,46 @@ +|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+
+*** Source file is address_decoder.tt4 . Device is M4-32/32-15JC .
+
+<Note> F35109: For this device, all input pairing is ignored since input
+ registers or latches do not exist. All signals must pass
+ through the central switch matrix before being latched or
+ registered.
+<Note> F40016: 0 pins have been reserved out of 34 .
+<Note> F40021: 34 pins are available after reservation, 21 are required
+ by the design.
+<Note> F35065: For outputs, implicit output enables will be set to VCC.
+
+*** End of Pla2db.
+Check preplaced pins/nodes
+Check preplaced blocks
+Check unreferenced pins/nodes
+Check clock rules
+
+List of non-global clocks:
+ None.
+
+*** End of Normalization.
+
+*** End of DRC.
+
+*** Start Partitioning
+
+*** Partitioning successful.
+
+
+*** Starting Place&Route
+
+*** Place&Route Successful
+*** The JEDEC file generated is address_decoder.jed .
+*** Report Generator invoked.
+*** Report Generator end.
+
+// Fitting successful.
+// ERROR count 0 WARNING count 0 .
diff --git a/sw/cpld/address_decoder.mod b/sw/cpld/address_decoder.mod new file mode 100755 index 0000000..8724fa0 --- /dev/null +++ b/sw/cpld/address_decoder.mod @@ -0,0 +1,58 @@ +MODEL
+MODEL_VERSION "1.0";
+DESIGN "address_decoder";
+DATE "Mon Nov 13 11:47:14 2017";
+VENDOR "Lattice Semiconductor Co. Ltd.";
+PROGRAM "STAMP Model Generator";
+
+/* port name and type */
+INPUT MMU_IN_2;
+INPUT MMU_IN_3;
+INPUT MMU_IN_4;
+INPUT MMU_IN_5;
+INPUT MMU_IN_6;
+INPUT MMU_IN_7;
+INPUT MMU_IN_8;
+INPUT MMU_IN_9;
+INPUT MMU_IN_10;
+INPUT MMU_IN_11;
+INPUT MMU_IN_12;
+INPUT MMU_IN_13;
+INPUT MMU_IN_14;
+INPUT MMU_IN_15;
+OUTPUT CSCTC;
+OUTPUT CSPIO;
+OUTPUT CSRAM;
+OUTPUT CSROMH;
+OUTPUT CSROML;
+OUTPUT CSUART;
+OUTPUT MMU_OUT_12;
+OUTPUT MMU_OUT_13;
+OUTPUT MMU_OUT_14;
+OUTPUT MMU_OUT_15;
+
+/* timing arc definitions */
+MMU_IN_2_CSUART_delay: DELAY MMU_IN_2 CSUART;
+MMU_IN_3_CSUART_delay: DELAY MMU_IN_3 CSUART;
+MMU_IN_4_CSUART_delay: DELAY MMU_IN_4 CSUART;
+MMU_IN_5_CSUART_delay: DELAY MMU_IN_5 CSUART;
+MMU_IN_6_CSUART_delay: DELAY MMU_IN_6 CSUART;
+MMU_IN_7_CSUART_delay: DELAY MMU_IN_7 CSUART;
+MMU_IN_8_CSCTC_delay: DELAY MMU_IN_8 CSCTC;
+MMU_IN_8_CSPIO_delay: DELAY MMU_IN_8 CSPIO;
+MMU_IN_8_CSUART_delay: DELAY MMU_IN_8 CSUART;
+MMU_IN_9_CSCTC_delay: DELAY MMU_IN_9 CSCTC;
+MMU_IN_9_CSPIO_delay: DELAY MMU_IN_9 CSPIO;
+MMU_IN_9_CSUART_delay: DELAY MMU_IN_9 CSUART;
+MMU_IN_10_CSCTC_delay: DELAY MMU_IN_10 CSCTC;
+MMU_IN_10_CSPIO_delay: DELAY MMU_IN_10 CSPIO;
+MMU_IN_10_CSUART_delay: DELAY MMU_IN_10 CSUART;
+MMU_IN_11_CSCTC_delay: DELAY MMU_IN_11 CSCTC;
+MMU_IN_11_CSPIO_delay: DELAY MMU_IN_11 CSPIO;
+MMU_IN_11_CSUART_delay: DELAY MMU_IN_11 CSUART;
+MMU_IN_12_CSCTC_delay: DELAY MMU_IN_12 CSCTC;
+MMU_IN_12_CSPIO_delay: DELAY MMU_IN_12 CSPIO;
+
+/* timing check arc definitions */
+
+ENDMODEL
diff --git a/sw/cpld/address_decoder.nrp b/sw/cpld/address_decoder.nrp new file mode 100755 index 0000000..6b40d36 --- /dev/null +++ b/sw/cpld/address_decoder.nrp @@ -0,0 +1,17 @@ +ispDesignExpert 8.3.02.12_DE_HDL_BASE Copyright ©, 1992-1999,
+Lattice Semiconductor Corporation, All Rights Reserved
+
+Output Files:
+ Netlist File: address_decoder.vho
+ Delay File: address_decoder.sdf
+
+Parsing C:\ISPTOOLS\ISPSYS/dat/sdf.mdl
+Input file: c:\_prossn\cpld\address_decoder.tte
+Reading library information ...
+Mapping to combinational gates
+Mapping to netlist view.
+Utilization Estimate
+ Combinational Macros: 27
+ Flip-Flop and Latch Macros: 0
+ I/O Pads: 24
+Elapsed time: 1 seconds
diff --git a/sw/cpld/address_decoder.out b/sw/cpld/address_decoder.out new file mode 100755 index 0000000..163d8a9 --- /dev/null +++ b/sw/cpld/address_decoder.out @@ -0,0 +1,437 @@ +
+19 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 CSRAM 0 0 0 -1 -1 2 0 21
+ 83 CSPIO 0 0 0 -1 -1 1 0 21
+ 82 CSCTC 0 1 0 -1 -1 1 0 21
+ 81 CSUART 0 0 0 -1 -1 1 0 21
+ 79 CSROML 0 1 0 -1 -1 1 0 21
+ 78 CSROMH 0 1 0 -1 -1 1 0 21
+ 93 PA_5_ 1 -1 -1 2 0 1 -1 -1
+ 92 PA_6_ 1 -1 -1 2 0 1 -1 -1
+ 91 PA_7_ 1 -1 -1 2 0 1 -1 -1
+ 90 PA_8_ 1 -1 -1 2 0 1 -1 -1
+ 89 PA_9_ 1 -1 -1 2 0 1 -1 -1
+ 88 PA_10_ 1 -1 -1 2 0 1 -1 -1
+ 87 PA_11_ 1 -1 -1 2 0 1 -1 -1
+ 86 PA_12_ 1 -1 -1 2 0 1 -1 -1
+ 85 PA_13_ 1 -1 -1 2 0 1 -1 -1
+ 84 PA_14_ 1 -1 -1 2 0 1 -1 -1
+ 77 PA_15_ 1 -1 -1 2 0 1 -1 -1
+ 95 PA_3_ 1 -1 -1 1 0 -1 -1
+ 94 PA_4_ 1 -1 -1 1 0 -1 -1
+19 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 CSRAM 0 0 0 -1 -1 2 0 21
+ 83 CSPIO 0 0 0 -1 -1 1 0 21
+ 82 CSCTC 0 1 0 -1 -1 1 0 21
+ 81 CSUART 0 0 0 -1 -1 1 0 21
+ 79 CSROML 0 1 0 -1 -1 1 0 21
+ 78 CSROMH 0 1 0 -1 -1 1 0 21
+ 93 PA_5_ 1 -1 -1 2 0 1 -1 -1
+ 92 PA_6_ 1 -1 -1 2 0 1 -1 -1
+ 91 PA_7_ 1 -1 -1 2 0 1 -1 -1
+ 90 PA_8_ 1 -1 -1 2 0 1 -1 -1
+ 89 PA_9_ 1 -1 -1 2 0 1 -1 -1
+ 88 PA_10_ 1 -1 -1 2 0 1 -1 -1
+ 87 PA_11_ 1 -1 -1 2 0 1 -1 -1
+ 86 PA_12_ 1 -1 -1 2 0 1 -1 -1
+ 85 PA_13_ 1 -1 -1 2 0 1 -1 -1
+ 84 PA_14_ 1 -1 -1 2 0 1 -1 -1
+ 77 PA_15_ 1 -1 -1 2 0 1 -1 -1
+ 95 PA_3_ 1 -1 -1 1 0 -1 -1
+ 94 PA_4_ 1 -1 -1 1 0 -1 -1
+22 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 PA_15_ 1 -1 -1 1 1 20 -1
+ 19 PA_14_ 1 -1 -1 1 1 19 -1
+ 18 PA_13_ 1 -1 -1 1 1 18 -1
+ 17 PA_12_ 1 -1 -1 1 1 17 -1
+ 16 PA_11_ 1 -1 -1 1 1 16 -1
+ 15 PA_10_ 1 -1 -1 1 1 15 -1
+ 14 PA_9_ 1 -1 -1 1 1 14 -1
+ 13 PA_8_ 1 -1 -1 1 1 13 -1
+ 8 PA_0_ 1 -1 -1 1 1 8 -1
+ 7 PA_1_ 1 -1 -1 1 1 7 -1
+ 6 PA_2_ 1 -1 -1 1 1 6 -1
+ 5 PA_3_ 1 -1 -1 1 1 5 -1
+ 4 PA_4_ 1 -1 -1 1 1 4 -1
+ 3 PA_5_ 1 -1 -1 1 1 3 -1
+ 2 PA_6_ 1 -1 -1 1 1 2 -1
+ 1 PA_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 25 CSRAM 0 1 0 25 -1 2 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+26 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 28 CSPIO 0 1 0 28 -1 3 0 21
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 8 MMU_IN_0_ 1 -1 -1 1 1 8 -1
+ 7 MMU_IN_1_ 1 -1 -1 1 1 7 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+18 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+25 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+ 77 IORQ 1 -1 -1 1 1 -1 -1
+25 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 30 IORQ 1 -1 -1 1 1 30 -1
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+24 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 16 MMU_IN_11_ 1 -1 -1 1 1 16 -1
+ 15 MMU_IN_10_ 1 -1 -1 1 1 15 -1
+ 14 MMU_IN_9_ 1 -1 -1 1 1 14 -1
+ 13 MMU_IN_8_ 1 -1 -1 1 1 13 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+21 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
+ 77 IORQ 1 -1 -1 1 1 -1 -1
+21 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 38 MMU_OUT_12_ 0 1 0 38 -1 1 0 21
+ 37 MMU_OUT_13_ 0 1 0 37 -1 1 0 21
+ 36 MMU_OUT_14_ 0 1 0 36 -1 1 0 21
+ 35 MMU_OUT_15_ 0 1 0 35 -1 1 0 21
+ 28 CSPIO 0 1 0 28 -1 1 0 21
+ 27 CSCTC 0 1 0 27 -1 1 0 21
+ 26 CSUART 0 1 0 26 -1 1 0 21
+ 25 CSRAM 0 1 0 25 -1 1 0 21
+ 24 CSROMH 0 1 0 24 -1 1 0 21
+ 23 CSROML 0 1 0 23 -1 1 0 21
+ 29 IORQ 1 -1 -1 1 1 29 -1
+ 20 MMU_IN_15_ 1 -1 -1 1 1 20 -1
+ 19 MMU_IN_14_ 1 -1 -1 1 1 19 -1
+ 18 MMU_IN_13_ 1 -1 -1 1 1 18 -1
+ 17 MMU_IN_12_ 1 -1 -1 1 1 17 -1
+ 6 MMU_IN_2_ 1 -1 -1 1 1 6 -1
+ 5 MMU_IN_3_ 1 -1 -1 1 1 5 -1
+ 4 MMU_IN_4_ 1 -1 -1 1 1 4 -1
+ 3 MMU_IN_5_ 1 -1 -1 1 1 3 -1
+ 2 MMU_IN_6_ 1 -1 -1 1 1 2 -1
+ 1 MMU_IN_7_ 1 -1 -1 1 1 1 -1
\ No newline at end of file diff --git a/sw/cpld/address_decoder.plc b/sw/cpld/address_decoder.plc new file mode 100755 index 0000000..1c799c1 --- /dev/null +++ b/sw/cpld/address_decoder.plc @@ -0,0 +1,36 @@ +|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+; Source file address_decoder.tt4
+; FITTER-generated Placements.
+; DEVICE mach432
+; DATE Thu Nov 23 11:55:45 2017
+
+
+Pin 2 MMU_IN_7_
+Pin 3 MMU_IN_6_
+Pin 21 MMU_IN_15_
+Pin 4 MMU_IN_5_
+Pin 5 MMU_IN_4_
+Pin 36 MMU_OUT_15_ Comb ; S6=1 S9=1 Pair 66
+Pin 6 MMU_IN_3_
+Pin 30 IORQ
+Pin 7 MMU_IN_2_
+Pin 24 CSROML Comb ; S6=1 S9=1 Pair 75
+Pin 25 CSROMH Comb ; S6=1 S9=1 Pair 71
+Pin 37 MMU_OUT_14_ Comb ; S6=1 S9=1 Pair 62
+Pin 26 CSRAM Comb ; S6=1 S9=1 Pair 74
+Pin 38 MMU_OUT_13_ Comb ; S6=1 S9=1 Pair 65
+Pin 27 CSUART Comb ; S6=1 S9=1 Pair 70
+Pin 39 MMU_OUT_12_ Comb ; S6=1 S9=1 Pair 61
+Pin 28 CSCTC Comb ; S6=1 S9=1 Pair 73
+Pin 29 CSPIO Comb ; S6=1 S9=1 Pair 69
+Pin 20 MMU_IN_14_
+Pin 19 MMU_IN_13_
+Pin 18 MMU_IN_12_
+; Unused Pins & Nodes
+; -> None Found.
diff --git a/sw/cpld/address_decoder.prd b/sw/cpld/address_decoder.prd new file mode 100755 index 0000000..4258471 --- /dev/null +++ b/sw/cpld/address_decoder.prd @@ -0,0 +1,464 @@ +|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+Start: Thu Nov 23 11:55:45 2017
+End : Thu Nov 23 11:55:45 2017 $$$ Elapsed time: 00:00:00
+===========================================================================
+Part [C:\ISPTOOLS\ISPSYS/dat/mach4/mach432] Design [address_decoder.tt4]
+
+* Place/Route options (keycode = 540674)
+ = Spread Placement: ON
+ = No. Routing Attempts/Placement 2
+
+* Placement Completion
+
+ +- Block +------- IO Pins Available
+ | +- Macrocells Available | +-- IO Pins Used
+ | | +- Signals to Place | | +----- Logic Array Inputs
+ | | | +- Placed | | | +- Array Inputs Used
+_|____|____|____|_______________|____|_____________|___|________________
+ 0 | 16 | 0 | 0 => n/a | 16 | 10 => 62% | 33 | 0 => 0%
+ 1 | 16 | 10 | 10 => 100% | 16 | 11 => 68% | 33 | 11 => 33%
+---|----|----|------------|-------|------------|-----|------------------
+ | Avg number of array inputs in used blocks : 11.00 => 33%
+
+* Input/Clock Signal count: 11 -> placed: 11 = 100%
+
+ Resources Available Used
+-----------------------------------------------------------------
+ Input Pins : 0 0 => 0%
+ I/O Pins : 32 21 => 65%
+ Clock Only Pins : 0 0 => 0%
+ Clock/Input Pins : 2 0 => 0%
+ Logic Blocks : 2 1 => 50%
+ Macrocells : 32 10 => 31%
+ PT Clusters : 32 0 => 0%
+ - Single PT Clusters : 32 10 => 31%
+ Input Registers : 0
+
+* Routing Completion: 100%
+* Attempts: Place [ 21] Route [ 0]
+===========================================================================
+ Signal Fanout Table
+===========================================================================
+ +- Signal Number
+ | +- Block Location ('+' for dedicated inputs)
+ | | +- Sig Type
+ | | | +- Signal-to-Pin Assignment
+ | | | | Fanout to Logic Blocks Signal Name
+___|__|__|____|____________________________________________________________
+ 1| 1|OUT| 28|=> ..| CSCTC
+ 2| 1|OUT| 29|=> ..| CSPIO
+ 3| 1|OUT| 26|=> ..| CSRAM
+ 4| 1|OUT| 25|=> ..| CSROMH
+ 5| 1|OUT| 24|=> ..| CSROML
+ 6| 1|OUT| 27|=> ..| CSUART
+ 7| 1|INP| 30|=> .1| IORQ
+ 8| 0|INP| 18|=> .1| MMU_IN_12_
+ 9| 0|INP| 19|=> .1| MMU_IN_13_
+ 10| 0|INP| 20|=> .1| MMU_IN_14_
+ 11| 0|INP| 21|=> .1| MMU_IN_15_
+ 12| 0|INP| 7|=> .1| MMU_IN_2_
+ 13| 0|INP| 6|=> .1| MMU_IN_3_
+ 14| 0|INP| 5|=> .1| MMU_IN_4_
+ 15| 0|INP| 4|=> .1| MMU_IN_5_
+ 16| 0|INP| 3|=> .1| MMU_IN_6_
+ 17| 0|INP| 2|=> .1| MMU_IN_7_
+ 18| 1|OUT| 39|=> ..| MMU_OUT_12_
+ 19| 1|OUT| 38|=> ..| MMU_OUT_13_
+ 20| 1|OUT| 37|=> ..| MMU_OUT_14_
+ 21| 1|OUT| 36|=> ..| MMU_OUT_15_
+---------------------------------------------------------------------------
+===========================================================================
+ < C:\ISPTOOLS\ISPSYS/dat/mach4/mach432 Device Pin Assignments >
+===========================================================================
+ +- Device Pin No
+ | Pin Type +- Signal Fixed (*)
+ | | | Signal Name
+____|_____|_________|______________________________________________________
+ 1 | GND | | | (pwr/test)
+ 2 | I_O | 0_07|*| MMU_IN_7_
+ 3 | I_O | 0_06|*| MMU_IN_6_
+ 4 | I_O | 0_05|*| MMU_IN_5_
+ 5 | I_O | 0_04|*| MMU_IN_4_
+ 6 | I_O | 0_03|*| MMU_IN_3_
+ 7 | I_O | 0_02|*| MMU_IN_2_
+ 8 | I_O | 0_01| | -
+ 9 | I_O | 0_00| | -
+ 10 | JTAG | | | (pwr/test)
+ 11 | CkIn | | | -
+ 12 | GND | | | (pwr/test)
+ 13 | JTAG | | | (pwr/test)
+ 14 | I_O | 0_08| | -
+ 15 | I_O | 0_09| | -
+ 16 | I_O | 0_10| | -
+ 17 | I_O | 0_11| | -
+ 18 | I_O | 0_12|*| MMU_IN_12_
+ 19 | I_O | 0_13|*| MMU_IN_13_
+ 20 | I_O | 0_14|*| MMU_IN_14_
+ 21 | I_O | 0_15|*| MMU_IN_15_
+ 22 | Vcc | | | (pwr/test)
+ 23 | GND | | | (pwr/test)
+ 24 | I_O | 1_15|*| CSROML
+ 25 | I_O | 1_14|*| CSROMH
+ 26 | I_O | 1_13|*| CSRAM
+ 27 | I_O | 1_12|*| CSUART
+ 28 | I_O | 1_11|*| CSCTC
+ 29 | I_O | 1_10|*| CSPIO
+ 30 | I_O | 1_09|*| IORQ
+ 31 | I_O | 1_08| | -
+ 32 | JTAG | | | (pwr/test)
+ 33 | CkIn | | | -
+ 34 | GND | | | (pwr/test)
+ 35 | JTAG | | | (pwr/test)
+ 36 | I_O | 1_00|*| MMU_OUT_15_
+ 37 | I_O | 1_01|*| MMU_OUT_14_
+ 38 | I_O | 1_02|*| MMU_OUT_13_
+ 39 | I_O | 1_03|*| MMU_OUT_12_
+ 40 | I_O | 1_04| | -
+ 41 | I_O | 1_05| | -
+ 42 | I_O | 1_06| | -
+ 43 | I_O | 1_07| | -
+ 44 | Vcc | | | (pwr/test)
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 0] > IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ | Device Pin No.--------+
+ | Pin Fixed(*)----+ |
+ | Sig Type--+ | | |
+ | Signal Name | | | | Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0| | | | 9| => | 0 1 2 3 4 5 6 7
+ 1| | | | 8| => | 1 2 3 4 5 6 7 0
+ 2| MMU_IN_2_|INP|*| 7| => | 2 3 4 5 6 7 0 1
+ 3| MMU_IN_3_|INP|*| 6| => | 3 4 5 6 7 0 1 2
+ 4| MMU_IN_4_|INP|*| 5| => | 4 5 6 7 0 1 2 3
+ 5| MMU_IN_5_|INP|*| 4| => | 5 6 7 0 1 2 3 4
+ 6| MMU_IN_6_|INP|*| 3| => | 6 7 0 1 2 3 4 5
+ 7| MMU_IN_7_|INP|*| 2| => | 7 0 1 2 3 4 5 6
+ 8| | | | 14| => | 8 9 10 11 12 13 14 15
+ 9| | | | 15| => | 9 10 11 12 13 14 15 8
+10| | | | 16| => | 10 11 12 13 14 15 8 9
+11| | | | 17| => | 11 12 13 14 15 8 9 10
+12| MMU_IN_12_|INP|*| 18| => | 12 13 14 15 8 9 10 11
+13| MMU_IN_13_|INP|*| 19| => | 13 14 15 8 9 10 11 12
+14| MMU_IN_14_|INP|*| 20| => | 14 15 8 9 10 11 12 13
+15| MMU_IN_15_|INP|*| 21| => | 15 8 9 10 11 12 13 14
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ | Device Pin No.--------+
+ | Pin Fixed(*)----+ |
+ | Sig Type--+ | | |
+ | Signal Name | | | | Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0| | | | 9| => | Input macrocell [ -]
+ 1| | | | 8| => | Input macrocell [ -]
+ 2| MMU_IN_2_|INP|*| 7| => | Input macrocell [ -]
+ 3| MMU_IN_3_|INP|*| 6| => | Input macrocell [ -]
+ 4| MMU_IN_4_|INP|*| 5| => | Input macrocell [ -]
+ 5| MMU_IN_5_|INP|*| 4| => | Input macrocell [ -]
+ 6| MMU_IN_6_|INP|*| 3| => | Input macrocell [ -]
+ 7| MMU_IN_7_|INP|*| 2| => | Input macrocell [ -]
+ 8| | | | 14| => | Input macrocell [ -]
+ 9| | | | 15| => | Input macrocell [ -]
+10| | | | 16| => | Input macrocell [ -]
+11| | | | 17| => | Input macrocell [ -]
+12| MMU_IN_12_|INP|*| 18| => | Input macrocell [ -]
+13| MMU_IN_13_|INP|*| 19| => | Input macrocell [ -]
+14| MMU_IN_14_|INP|*| 20| => | Input macrocell [ -]
+15| MMU_IN_15_|INP|*| 21| => | Input macrocell [ -]
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 0] > Input Multiplexer (IMX) Assignments
+===========================================================================
+ +----- IO pin/Input Register, or Macrocell
+IMX No. | +---- Block IO Pin or Macrocell Number
+ | | | ABEL Node/ +-- Signal using the Pin or Macrocell
+ | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
+ | | | | Sig Type | | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+ 0 [IOpin 0 | 9| -| | ]
+ [MCell 0 | 45| -| | ]
+
+ 1 [IOpin 1 | 8| -| | ]
+ [MCell 1 | 46| -| | ]
+
+ 2 [IOpin 2 | 7|INP MMU_IN_2_|*|*]
+ [MCell 2 | 47| -| | ]
+
+ 3 [IOpin 3 | 6|INP MMU_IN_3_|*|*]
+ [MCell 3 | 48| -| | ]
+
+ 4 [IOpin 4 | 5|INP MMU_IN_4_|*|*]
+ [MCell 4 | 49| -| | ]
+
+ 5 [IOpin 5 | 4|INP MMU_IN_5_|*|*]
+ [MCell 5 | 50| -| | ]
+
+ 6 [IOpin 6 | 3|INP MMU_IN_6_|*|*]
+ [MCell 6 | 51| -| | ]
+
+ 7 [IOpin 7 | 2|INP MMU_IN_7_|*|*]
+ [MCell 7 | 52| -| | ]
+
+ 8 [IOpin 8 | 14| -| | ]
+ [MCell 8 | 53| -| | ]
+
+ 9 [IOpin 9 | 15| -| | ]
+ [MCell 9 | 54| -| | ]
+
+ 10 [IOpin 10 | 16| -| | ]
+ [MCell 10 | 55| -| | ]
+
+ 11 [IOpin 11 | 17| -| | ]
+ [MCell 11 | 56| -| | ]
+
+ 12 [IOpin 12 | 18|INP MMU_IN_12_|*|*]
+ [MCell 12 | 57| -| | ]
+
+ 13 [IOpin 13 | 19|INP MMU_IN_13_|*|*]
+ [MCell 13 | 58| -| | ]
+
+ 14 [IOpin 14 | 20|INP MMU_IN_14_|*|*]
+ [MCell 14 | 59| -| | ]
+
+ 15 [IOpin 15 | 21|INP MMU_IN_15_|*|*]
+ [MCell 15 | 60| -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
+ | Sync/Async-------+ | | | Cluster to Mcell Assignment
+ | Node Fixed(*)----+ | | | | | +- XOR PT Size
+ | Sig Type-+ | | | | | | | XOR to Mcell Assignment
+ | Signal Name | | | | | | | | |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0| MMU_OUT_12_|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
+ 1| MMU_OUT_14_|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
+ 2| | ? | | S | | 4 free | 1 XOR free
+ 3| | ? | | S | | 4 free | 1 XOR free
+ 4| MMU_OUT_13_|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig
+ 5| MMU_OUT_15_|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig
+ 6| | ? | | S | | 4 free | 1 XOR free
+ 7| | ? | | S | | 4 free | 1 XOR free
+ 8| CSPIO|OUT| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
+ 9| CSUART|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig
+10| CSROMH|OUT| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig
+11| | ? | | S | | 4 free | 1 XOR free
+12| CSCTC|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
+13| CSRAM|OUT| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig
+14| CSROML|OUT| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig
+15| | ? | | S | | 4 free | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic XOR+
+ | Sync/Async-------+ | |
+ | Node Fixed(*)----+ | | |
+ | Sig Type-+ | | | |
+ | Signal Name | | | | | Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0| MMU_OUT_12_|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
+ 1| MMU_OUT_14_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
+ 2| | ? | | S | |=> can support up to [ 18] logic PT(s)
+ 3| | ? | | S | |=> can support up to [ 18] logic PT(s)
+ 4| MMU_OUT_13_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
+ 5| MMU_OUT_15_|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
+ 6| | ? | | S | |=> can support up to [ 14] logic PT(s)
+ 7| | ? | | S | |=> can support up to [ 10] logic PT(s)
+ 8| CSPIO|OUT| | S | 1 |=> can support up to [ 13] logic PT(s)
+ 9| CSUART|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
+10| CSROMH|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
+11| | ? | | S | |=> can support up to [ 17] logic PT(s)
+12| CSCTC|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
+13| CSRAM|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
+14| CSROML|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
+15| | ? | | S | |=> can support up to [ 9] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin
+ | Signal Name | | pin | Numbers | Numbers
+_|_________________|__|_____|____________________|________________________
+ 0| MMU_OUT_12_|OUT| | => | 0 1 2 ( 3) 4 5 6 7 | 36 37 38 ( 39) 40 41 42 43
+ 1| MMU_OUT_14_|OUT| | => | 0 ( 1) 2 3 4 5 6 7 | 36 ( 37) 38 39 40 41 42 43
+ 2| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
+ 3| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
+ 4| MMU_OUT_13_|OUT| | => | 0 1 ( 2) 3 4 5 6 7 | 36 37 ( 38) 39 40 41 42 43
+ 5| MMU_OUT_15_|OUT| | => |( 0) 1 2 3 4 5 6 7 |( 36) 37 38 39 40 41 42 43
+ 6| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
+ 7| | | | => | 0 1 2 3 4 5 6 7 | 36 37 38 39 40 41 42 43
+ 8| CSPIO|OUT| | => | 8 9 ( 10) 11 12 13 14 15 | 31 30 ( 29) 28 27 26 25 24
+ 9| CSUART|OUT| | => | 8 9 10 11 ( 12) 13 14 15 | 31 30 29 28 ( 27) 26 25 24
+10| CSROMH|OUT| | => | 8 9 10 11 12 13 ( 14) 15 | 31 30 29 28 27 26 ( 25) 24
+11| | | | => | 8 9 10 11 12 13 14 15 | 31 30 29 28 27 26 25 24
+12| CSCTC|OUT| | => | 8 9 10 ( 11) 12 13 14 15 | 31 30 29 ( 28) 27 26 25 24
+13| CSRAM|OUT| | => | 8 9 10 11 12 ( 13) 14 15 | 31 30 29 28 27 ( 26) 25 24
+14| CSROML|OUT| | => | 8 9 10 11 12 13 14 ( 15)| 31 30 29 28 27 26 25 ( 24)
+15| | | | => | 8 9 10 11 12 13 14 15 | 31 30 29 28 27 26 25 24
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ | Device Pin No.--------+
+ | Pin Fixed(*)----+ |
+ | Sig Type--+ | | |
+ | Signal Name | | | | Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0| MMU_OUT_15_|OUT|*| 36| => | 0 1 2 3 4 ( 5) 6 7
+ 1| MMU_OUT_14_|OUT|*| 37| => | ( 1) 2 3 4 5 6 7 0
+ 2| MMU_OUT_13_|OUT|*| 38| => | 2 3 ( 4) 5 6 7 0 1
+ 3| MMU_OUT_12_|OUT|*| 39| => | 3 4 5 6 7 ( 0) 1 2
+ 4| | | | 40| => | 4 5 6 7 0 1 2 3
+ 5| | | | 41| => | 5 6 7 0 1 2 3 4
+ 6| | | | 42| => | 6 7 0 1 2 3 4 5
+ 7| | | | 43| => | 7 0 1 2 3 4 5 6
+ 8| | | | 31| => | 8 9 10 11 12 13 14 15
+ 9| IORQ|INP|*| 30| => | 9 10 11 12 13 14 15 8
+10| CSPIO|OUT|*| 29| => | 10 11 12 13 14 15 ( 8) 9
+11| CSCTC|OUT|*| 28| => | 11 (12) 13 14 15 8 9 10
+12| CSUART|OUT|*| 27| => | 12 13 14 15 8 ( 9) 10 11
+13| CSRAM|OUT|*| 26| => | (13) 14 15 8 9 10 11 12
+14| CSROMH|OUT|*| 25| => | 14 15 8 9 (10) 11 12 13
+15| CSROML|OUT|*| 24| => | 15 8 9 10 11 12 13 (14)
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ | Device Pin No.--------+
+ | Pin Fixed(*)----+ |
+ | Sig Type--+ | | |
+ | Signal Name | | | | Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0| MMU_OUT_15_|OUT|*| 36| => | Input macrocell [ -]
+ 1| MMU_OUT_14_|OUT|*| 37| => | Input macrocell [ -]
+ 2| MMU_OUT_13_|OUT|*| 38| => | Input macrocell [ -]
+ 3| MMU_OUT_12_|OUT|*| 39| => | Input macrocell [ -]
+ 4| | | | 40| => | Input macrocell [ -]
+ 5| | | | 41| => | Input macrocell [ -]
+ 6| | | | 42| => | Input macrocell [ -]
+ 7| | | | 43| => | Input macrocell [ -]
+ 8| | | | 31| => | Input macrocell [ -]
+ 9| IORQ|INP|*| 30| => | Input macrocell [ -]
+10| CSPIO|OUT|*| 29| => | Input macrocell [ -]
+11| CSCTC|OUT|*| 28| => | Input macrocell [ -]
+12| CSUART|OUT|*| 27| => | Input macrocell [ -]
+13| CSRAM|OUT|*| 26| => | Input macrocell [ -]
+14| CSROMH|OUT|*| 25| => | Input macrocell [ -]
+15| CSROML|OUT|*| 24| => | Input macrocell [ -]
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > Input Multiplexer (IMX) Assignments
+===========================================================================
+ +----- IO pin/Input Register, or Macrocell
+IMX No. | +---- Block IO Pin or Macrocell Number
+ | | | ABEL Node/ +-- Signal using the Pin or Macrocell
+ | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
+ | | | | Sig Type | | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+ 0 [IOpin 0 | 36|OUT MMU_OUT_15_|*| ]
+ [MCell 0 | 61|OUT MMU_OUT_12_| | ]
+
+ 1 [IOpin 1 | 37|OUT MMU_OUT_14_|*| ]
+ [MCell 1 | 62|OUT MMU_OUT_14_| | ]
+
+ 2 [IOpin 2 | 38|OUT MMU_OUT_13_|*| ]
+ [MCell 2 | 63| -| | ]
+
+ 3 [IOpin 3 | 39|OUT MMU_OUT_12_|*| ]
+ [MCell 3 | 64| -| | ]
+
+ 4 [IOpin 4 | 40| -| | ]
+ [MCell 4 | 65|OUT MMU_OUT_13_| | ]
+
+ 5 [IOpin 5 | 41| -| | ]
+ [MCell 5 | 66|OUT MMU_OUT_15_| | ]
+
+ 6 [IOpin 6 | 42| -| | ]
+ [MCell 6 | 67| -| | ]
+
+ 7 [IOpin 7 | 43| -| | ]
+ [MCell 7 | 68| -| | ]
+
+ 8 [IOpin 8 | 31| -| | ]
+ [MCell 8 | 69|OUT CSPIO| | ]
+
+ 9 [IOpin 9 | 30|INP IORQ|*|*]
+ [MCell 9 | 70|OUT CSUART| | ]
+
+ 10 [IOpin 10 | 29|OUT CSPIO|*| ]
+ [MCell 10 | 71|OUT CSROMH| | ]
+
+ 11 [IOpin 11 | 28|OUT CSCTC|*| ]
+ [MCell 11 | 72| -| | ]
+
+ 12 [IOpin 12 | 27|OUT CSUART|*| ]
+ [MCell 12 | 73|OUT CSCTC| | ]
+
+ 13 [IOpin 13 | 26|OUT CSRAM|*| ]
+ [MCell 13 | 74|OUT CSRAM| | ]
+
+ 14 [IOpin 14 | 25|OUT CSROMH|*| ]
+ [MCell 14 | 75|OUT CSROML| | ]
+
+ 15 [IOpin 15 | 24|OUT CSROML|*| ]
+ [MCell 15 | 76| -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+ < Block [ 1] > Logic Array Fan-in
+===========================================================================
+ +- Central Switch Matrix No.
+ | Src (ABEL Node/Pin#) Signal
+--|--|--------------------|---------------------------------------------------
+Mux00| IOPin 0 7 ( 2)| MMU_IN_7_
+Mux01| IOPin 0 4 ( 5)| MMU_IN_4_
+Mux02| ... | ...
+Mux03| ... | ...
+Mux04| ... | ...
+Mux05| ... | ...
+Mux06| IOPin 0 6 ( 3)| MMU_IN_6_
+Mux07| IOPin 0 3 ( 6)| MMU_IN_3_
+Mux08| IOPin 0 15 ( 21)| MMU_IN_15_
+Mux09| IOPin 0 5 ( 4)| MMU_IN_5_
+Mux10| IOPin 0 12 ( 18)| MMU_IN_12_
+Mux11| ... | ...
+Mux12| IOPin 0 13 ( 19)| MMU_IN_13_
+Mux13| IOPin 1 9 ( 30)| IORQ
+Mux14| ... | ...
+Mux15| IOPin 0 14 ( 20)| MMU_IN_14_
+Mux16| ... | ...
+Mux17| ... | ...
+Mux18| IOPin 0 2 ( 7)| MMU_IN_2_
+Mux19| ... | ...
+Mux20| ... | ...
+Mux21| ... | ...
+Mux22| ... | ...
+Mux23| ... | ...
+Mux24| ... | ...
+Mux25| ... | ...
+Mux26| ... | ...
+Mux27| ... | ...
+Mux28| ... | ...
+Mux29| ... | ...
+Mux30| ... | ...
+Mux31| ... | ...
+Mux32| ... | ...
+---------------------------------------------------------------------------
\ No newline at end of file diff --git a/sw/cpld/address_decoder.rev b/sw/cpld/address_decoder.rev deleted file mode 100644 index e8bfb3d..0000000 --- a/sw/cpld/address_decoder.rev +++ /dev/null @@ -1,3 +0,0 @@ -<SYNPROJ_Revision_Control> -<RevisionControl_Info/> -</SYNPROJ_Revision_Control> diff --git a/sw/cpld/address_decoder.rpt b/sw/cpld/address_decoder.rpt new file mode 100755 index 0000000..ecad5be --- /dev/null +++ b/sw/cpld/address_decoder.rpt @@ -0,0 +1,452 @@ +|--------------------------------------------|
+|- ispDesignExpert Fitter Report File -|
+|- Version 8.3.02.12_DE_HDL_BASE -|
+|- (c)Copyright, Lattice Semiconductor 1999 -|
+|--------------------------------------------|
+
+
+
+
+Project_Summary
+~~~~~~~~~~~~~~~
+
+Project Name : address_decoder
+Project Path : C:\_prossn\cpld.nao
+Project Fitted on : Thu Nov 23 11:55:45 2017
+
+Device : M4-32/32
+Package : 44PLCC
+Speed : -15
+Partnumber : M4-32/32-15JC
+Source Format : ABEL_Schematic
+
+
+// Project 'address_decoder' was Fitted Successfully! //
+
+
+Compilation_Times
+~~~~~~~~~~~~~~~~~
+Reading/DRC 0 sec
+Partition 0 sec
+Place 0 sec
+Route 0 sec
+Jedec/Report generation 0 sec
+ --------
+Fitter 00:00:00
+
+
+Design_Summary
+~~~~~~~~~~~~~~
+ Total Input Pins : 11
+ Total Output Pins : 10
+ Total Bidir I/O Pins : 0
+ Total Flip-Flops : 0
+ Total Product Terms : 10
+ Total Reserved Pins : 0
+ Total Reserved Blocks : 0
+
+
+Device_Resource_Summary
+~~~~~~~~~~~~~~~~~~~~~~~
+ Total
+ Available Used Available Utilization
+Dedicated Pins
+ Input-Only Pins .. .. .. --> ..
+ Clock/Input Pins 2 0 2 --> 0%
+I/O Pins 32 21 11 --> 65%
+Logic Macrocells 32 10 22 --> 31%
+ Unusable Macrocells .. 0 ..
+
+CSM Outputs/Total Block Inputs 66 11 55 --> 16%
+Logical Product Terms 160 10 150 --> 6%
+Product Term Clusters 32 0 32 --> 0%
+
+
+Blocks_Resource_Summary
+~~~~~~~~~~~~~~~~~~~~~~~
+ # of PT
+ I/O Macrocells Macrocells logic clusters
+ Fanin Pins Used Unusable available PTs available Pwr
+---------------------------------------------------------------------------------
+Maximum 33 16 -- -- 16 80 16 -
+---------------------------------------------------------------------------------
+Block A 0 10 0 0 16 0 16 Hi
+Block B 11 11 10 0 6 10 16 Hi
+---------------------------------------------------------------------------------
+
+<Note> Four rightmost columns above reflect last status of the placement process.
+<Note> Pwr (Power) : Hi = High
+ Lo = Low.
+
+
+Optimizer_and_Fitter_Options
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Pin Assignment : Yes
+Group Assignment : No
+Pin Reservation : No (1)
+Block Reservation : No
+
+@Ignore_Project_Constraints :
+ Pin Assignments : No
+ Keep Block Assignment --
+ Keep Segment Assignment --
+ Group Assignments : No
+ Macrocell Assignment : No
+ Keep Block Assignment --
+ Keep Segment Assignment --
+
+@Backannotate_Project_Constraints
+ Pin Assignments : No
+ Pin And Block Assignments : No
+ Pin, Macrocell and Block : No
+
+@Timing_Constraints : No
+
+@Global_Project_Optimization :
+ Balanced Partitioning : Yes
+ Spread Placement : Yes
+
+ Note :
+ Pack Design :
+ Balanced Partitioning = No
+ Spread Placement = No
+ Spread Design :
+ Balanced Partitioning = Yes
+ Spread Placement = Yes
+
+@Logic_Synthesis :
+ Logic Reduction : Yes
+ Node Collapsing : Yes
+ D/T Synthesis : Yes
+ Clock Optimization : No
+ Input Register Optimization : Yes
+ XOR Synthesis : Yes
+ Max. P-Term for Collapsing : 16
+ Max. P-Term for Splitting : 16
+ Max. Equation Fanin : 32
+ Keep Xor : Yes
+
+@Utilization_options
+ Max. % of macrocells used : 100
+ Max. % of block inputs used : 100
+ Max. % of segment lines used : ---
+ Max. % of macrocells used : ---
+
+
+@Import_Source_Constraint_Option No
+
+@Zero_Hold_Time No
+
+@Pull_up No
+
+@User_Signature 0
+
+@Output_Slew_Rate Default = Fast(2)
+
+@Power Default = High(2)
+
+
+Device Options:
+<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
+ follow the drive level set for the Global Configure Unused I/O Option.
+<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
+ Bidir and Burried Signal Lists.
+
+
+
+
+Pinout_Listing
+~~~~~~~~~~~~~~
+ | Pin |Blk |Assigned|
+Pin No| Type |Pad |Pin | Signal name
+---------------------------------------------------------------
+ 1 | GND | | |
+ 2 | I_O | A7 | * |MMU_IN_7_
+3 | I_O | A6 | * |MMU_IN_6_
+4 | I_O | A5 | * |MMU_IN_5_
+5 | I_O | A4 | * |MMU_IN_4_
+6 | I_O | A3 | * |MMU_IN_3_
+7 | I_O | A2 | * |MMU_IN_2_
+8 | I_O | A1 | |
+9 | I_O | A0 | |
+10 | JTAG | | |
+11 | CkIn | | |
+12 | GND | | |
+13 | JTAG | | |
+14 | I_O | A8 | |
+15 | I_O | A9 | |
+16 | I_O | A10| |
+17 | I_O | A11| |
+18 | I_O | A12| * |MMU_IN_12_
+19 | I_O | A13| * |MMU_IN_13_
+20 | I_O | A14| * |MMU_IN_14_
+21 | I_O | A15| * |MMU_IN_15_
+22 | Vcc | | |
+23 | GND | | |
+24 | I_O | B15| * |CSROML
+25 | I_O | B14| * |CSROMH
+26 | I_O | B13| * |CSRAM
+27 | I_O | B12| * |CSUART
+28 | I_O | B11| * |CSCTC
+29 | I_O | B10| * |CSPIO
+30 | I_O | B9 | * |IORQ
+31 | I_O | B8 | |
+32 | JTAG | | |
+33 | CkIn | | |
+34 | GND | | |
+35 | JTAG | | |
+36 | I_O | B0 | * |MMU_OUT_15_
+37 | I_O | B1 | * |MMU_OUT_14_
+38 | I_O | B2 | * |MMU_OUT_13_
+39 | I_O | B3 | * |MMU_OUT_12_
+40 | I_O | B4 | |
+41 | I_O | B5 | |
+42 | I_O | B6 | |
+43 | I_O | B7 | |
+44 | Vcc | | |
+
+---------------------------------------------------------------------------
+
+<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
+<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
+<Note> Pin Type :
+ CkIn : Dedicated input or clock pin
+ CLK : Dedicated clock pin
+ INP : Dedicated input pin
+ JTAG : JTAG Control and test pin
+ NC : No connected
+
+
+
+Input_Signal_List
+~~~~~~~~~~~~~~~~~
+ P R
+ Pin r e O Input
+Pin Blk PTs Type e s E Fanout Pwr Slew Signal
+----------------------------------------------------------------------
+ 30 B . I/O -B Hi Fast IORQ
+ 18 A . I/O -B Hi Fast MMU_IN_12_
+ 19 A . I/O -B Hi Fast MMU_IN_13_
+ 20 A . I/O -B Hi Fast MMU_IN_14_
+ 21 A . I/O -B Hi Fast MMU_IN_15_
+ 7 A . I/O -B Hi Fast MMU_IN_2_
+ 6 A . I/O -B Hi Fast MMU_IN_3_
+ 5 A . I/O -B Hi Fast MMU_IN_4_
+ 4 A . I/O -B Hi Fast MMU_IN_5_
+ 3 A . I/O -B Hi Fast MMU_IN_6_
+ 2 A . I/O -B Hi Fast MMU_IN_7_
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+ MH = Medium High
+ ML = Medium Low
+ Lo = Low
+
+
+
+Output_Signal_List
+~~~~~~~~~~~~~~~~~~
+ P R
+ Pin r e O Output
+Pin Blk PTs Type e s E Fanout Pwr Slew Signal
+----------------------------------------------------------------------
+ 28 B 1 COM -- Hi Fast CSCTC
+ 29 B 1 COM -- Hi Fast CSPIO
+ 26 B 1 COM -- Hi Fast CSRAM
+ 25 B 1 COM -- Hi Fast CSROMH
+ 24 B 1 COM -- Hi Fast CSROML
+ 27 B 1 COM -- Hi Fast CSUART
+ 39 B 1 COM -- Hi Fast MMU_OUT_12_
+ 38 B 1 COM -- Hi Fast MMU_OUT_13_
+ 37 B 1 COM -- Hi Fast MMU_OUT_14_
+ 36 B 1 COM -- Hi Fast MMU_OUT_15_
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+ MH = Medium High
+ ML = Medium Low
+ Lo = Low
+
+
+
+Bidir_Signal_List
+~~~~~~~~~~~~~~~~~
+ P R
+ Pin r e O Bidir
+Pin Blk PTs Type e s E Fanout Pwr Slew Signal
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+ MH = Medium High
+ ML = Medium Low
+ Lo = Low
+
+
+
+Buried_Signal_List
+~~~~~~~~~~~~~~~~~~
+ P R
+ Pin r e O Node
+#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
+----------------------------------------------------------------------
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+ MH = Medium High
+ ML = Medium Low
+ Lo = Low
+
+
+
+
+Signals_Fanout_List
+~~~~~~~~~~~~~~~~~~~
+Signal Source : Fanout List
+-----------------------------------------------------------------------------
+ MMU_IN_7_{ B}: CSPIO{ B}
+ MMU_IN_6_{ B}: CSPIO{ B}
+ MMU_IN_15_{ B}: MMU_OUT_15_{ B} CSROML{ B} CSROMH{ B}
+ : CSRAM{ B}
+ MMU_IN_5_{ B}: CSPIO{ B}
+ MMU_IN_4_{ B}: CSPIO{ B}
+ MMU_IN_3_{ B}: CSPIO{ B}
+ IORQ{ C}: CSPIO{ B}
+ MMU_IN_2_{ B}: CSPIO{ B}
+ MMU_IN_14_{ B}: CSROML{ B} CSROMH{ B} MMU_OUT_14_{ B}
+ MMU_IN_13_{ B}: CSROML{ B} CSROMH{ B} MMU_OUT_13_{ B}
+ MMU_IN_12_{ B}: MMU_OUT_12_{ B}
+-----------------------------------------------------------------------------
+
+<Note> {.} : Indicates block location of signal
+
+
+Set_Reset_Summary
+~~~~~~~~~~~~~~~~~
+
+Block A
+block level set pt :
+block level reset pt :
+Equations :
+| | |Block|Block| Signal
+| Reg |Mode |Set |Reset| Name
++-----+-----+-----+-----+------------------------
+| | | | | MMU_IN_15_
+| | | | | MMU_IN_14_
+| | | | | MMU_IN_13_
+| | | | | MMU_IN_12_
+| | | | | MMU_IN_2_
+| | | | | MMU_IN_3_
+| | | | | MMU_IN_4_
+| | | | | MMU_IN_5_
+| | | | | MMU_IN_6_
+| | | | | MMU_IN_7_
+
+
+Block B
+block level set pt :
+block level reset pt :
+Equations :
+| | |Block|Block| Signal
+| Reg |Mode |Set |Reset| Name
++-----+-----+-----+-----+------------------------
+| | | | | MMU_OUT_12_
+| | | | | MMU_OUT_13_
+| | | | | MMU_OUT_14_
+| | | | | MMU_OUT_15_
+| | | | | CSPIO
+| | | | | CSCTC
+| | | | | CSUART
+| | | | | CSRAM
+| | | | | CSROMH
+| | | | | CSROML
+| | | | | IORQ
+
+
+<Note> (S) means the macrocell is configured in synchronous mode
+ i.e. it uses the block-level set and reset pt.
+ (A) means the macrocell is configured in asynchronous mode
+ i.e. it can have its independant set or reset pt.
+ (BS) means the block-level set pt is selected.
+ (BR) means the block-level reset pt is selected.
+
+
+
+
+BLOCK_B_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM Signal Source CSM Signal Source
+------------------------------------ ------------------------------------
+mx B0 MMU_IN_7_ pin 2 mx B17 ... ...
+mx B1 MMU_IN_4_ pin 5 mx B18 MMU_IN_2_ pin 7
+mx B2 ... ... mx B19 ... ...
+mx B3 ... ... mx B20 ... ...
+mx B4 ... ... mx B21 ... ...
+mx B5 ... ... mx B22 ... ...
+mx B6 MMU_IN_6_ pin 3 mx B23 ... ...
+mx B7 MMU_IN_3_ pin 6 mx B24 ... ...
+mx B8 MMU_IN_15_ pin 21 mx B25 ... ...
+mx B9 MMU_IN_5_ pin 4 mx B26 ... ...
+mx B10 MMU_IN_12_ pin 18 mx B27 ... ...
+mx B11 ... ... mx B28 ... ...
+mx B12 MMU_IN_13_ pin 19 mx B29 ... ...
+mx B13 IORQ pin 30 mx B30 ... ...
+mx B14 ... ... mx B31 ... ...
+mx B15 MMU_IN_14_ pin 20 mx B32 ... ...
+mx B16 ... ...
+----------------------------------------------------------------------------
+
+<Note> CSM indicates the mux inputs from the Central Switch Matrix.
+<Note> Source indicates where the signal comes from (pin or macrocell).
+
+
+
+
+PostFit_Equations
+~~~~~~~~~~~~~~~~~
+
+
+ P-Terms Fan-in Fan-out Type Name (attributes)
+--------- ------ ------- ---- -----------------
+ 1 1 1 Pin MMU_OUT_15_
+ 1 3 1 Pin CSROML-
+ 1 3 1 Pin CSROMH-
+ 1 1 1 Pin MMU_OUT_14_
+ 1 1 1 Pin CSRAM
+ 1 1 1 Pin MMU_OUT_13_
+ 0 0 1 Pin CSUART
+ 1 1 1 Pin MMU_OUT_12_
+ 0 0 1 Pin CSCTC
+ 1 7 1 Pin CSPIO-
+=========
+ 8 P-Term Total: 8
+ Total Pins: 21
+ Total Nodes: 0
+ Average P-Term/Output: 0
+
+
+Equations:
+
+MMU_OUT_15_ = (MMU_IN_15_);
+
+!CSROML = (!MMU_IN_15_ & !MMU_IN_14_ & !MMU_IN_13_);
+
+!CSROMH = (!MMU_IN_15_ & !MMU_IN_14_ & MMU_IN_13_);
+
+MMU_OUT_14_ = (MMU_IN_14_);
+
+CSRAM = (!MMU_IN_15_);
+
+MMU_OUT_13_ = (MMU_IN_13_);
+
+CSUART = (0);
+
+MMU_OUT_12_ = (MMU_IN_12_);
+
+CSCTC = (0);
+
+!CSPIO = (!IORQ & !MMU_IN_7_ & !MMU_IN_6_ & !MMU_IN_5_ & MMU_IN_4_ & !MMU_IN_3_ & !MMU_IN_2_);
+
+
+Reverse-Polarity Equations:
+
diff --git a/sw/cpld/address_decoder.rs2 b/sw/cpld/address_decoder.rs2 new file mode 100755 index 0000000..431754c --- /dev/null +++ b/sw/cpld/address_decoder.rs2 @@ -0,0 +1 @@ +-inp "address_decoder.tt4" -vci "address_decoder.vct" -typ pla -mod loc -dir "c:\_prossn\cpld.nao" -DP1 eq3 -DP2 eq3 -lab Constraint#Editor -ntyp BLIF -nfile "address_decoder.bl2" -DP3 bl2 -ntyp BLIF -nfile "address_decoder.bl2" -DP3 bl2
diff --git a/sw/cpld/address_decoder.rs3 b/sw/cpld/address_decoder.rs3 new file mode 100755 index 0000000..1ec4e71 --- /dev/null +++ b/sw/cpld/address_decoder.rs3 @@ -0,0 +1 @@ +-inp "address_decoder.tt4" -vci "address_decoder.vco" -typ pla -mod nil -lab Post-Fit#Pinouts
diff --git a/sw/cpld/address_decoder.sdf b/sw/cpld/address_decoder.sdf new file mode 100755 index 0000000..3823d8f --- /dev/null +++ b/sw/cpld/address_decoder.sdf @@ -0,0 +1,204 @@ +// SDF delay-file
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "address_decoder")
+ (DATE "11/13/2017 11:47:12")
+ (VENDOR "Lattice Semiconductor")
+ (PROGRAM "SDF Generator")
+ (VERSION "8.3.02.12_DE_HDL_BASE Data sheet version: 1.01")
+ (DIVIDER /)
+ (VOLTAGE :5.0:)
+ (PROCESS "typical")
+ (TEMPERATURE :25:)
+ (TIMESCALE 100ps)
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_15_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSROML_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSROMH_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSRAM_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSUART_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSCTC_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_CSPIO_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_14_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_13_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "OBUF")
+ (INSTANCE OUT_MMU_OUT_12_I_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH I0 O (20:20:20) (20:20:20) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_15_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSRAM_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_14_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_13_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "BUFF")
+ (INSTANCE GATE_MMU_OUT_12_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSROML_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSROMH_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSUART_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSCTC_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "INV")
+ (INSTANCE GATE_CSPIO_I_1)
+ (DELAY
+ (ABSOLUTE
+ (PORT I0 (0:0:0) (0:0:0) )
+ (IOPATH I0 O (130:130:130) (130:130:130) )
+ )
+ )
+ )
+)
diff --git a/sw/cpld/address_decoder.srm b/sw/cpld/address_decoder.srm new file mode 100755 index 0000000..650d915 --- /dev/null +++ b/sw/cpld/address_decoder.srm @@ -0,0 +1,212 @@ +f "noname"; #file 0
+f "c:\isptools\synpbase\lib\vhd\std.vhd"; #file 1
+f "c:\_prossn\cpld.nao\address_decoder.vhd"; #file 2
+f "c:\isptools\synpbase\lib\vhd\std1164.vhd"; #file 3
+f "c:\isptools\synpbase\lib\vhd\arith.vhd"; #file 4
+f "c:\isptools\synpbase\lib\vhd\unsigned.vhd"; #file 5
+@ERMRlENORzQAwsRbH
+l;N3PRHs#bH4lR;R
+FmN;
+HbR3F8s0H"sRF"k0;R
+HQ
+j;N3HRb0Fs8RHs""HM;R
+bfjj:RVLkRmmRR;Qj
+fbRjR:j0CskRk0sCsR0k
+C;bjRf:VjRNCD#RDVN#VCRNCD#;R
+MROlNEARmzbwRs;Hl
+RNP3bH#sRHl4F;
+R
+m;N3HRb0Fs8RHs"0Fk"H;
+R;Qj
+RNH3sbF0s8HRM"H"b;
+R:fjjkRLVRRmmjRQ;R
+bfjj:Rk0sCsR0k0CRs;kC
+fbRjR:jV#NDCNRVDR#CV#NDCM;
+RNRlOqERhR7.blsH;P
+NR#3HblsHR
+4;F;Rm
+RNH3sbF0s8HRk"F0
+";HjRQ;H
+NRF3bsH08sHR"M
+";H4RQ;H
+NRF3bsH08sHR"M
+";bjRf:0jRsRkC0CskRk0sCb;
+R:fjjNRVDR#CV#NDCNRVD;#C
+fbRjR:jNPM8RmmRRRQjQ
+4;MlRRNROEQRheblsH;P
+NR#3HblsHR
+4;F;Rm
+RNH3sbF0s8HRk"F0
+";HjRQ;H
+NRF3bsH08sHR"M
+";bjRf:HjRMmPRRQmRjb;
+R:fjjsR0k0CRsRkC0Csk;R
+bfjj:RDVN#VCRNCD#RDVN#
+C;M@R@.::n(::n.R4RI FsR7q7)1 1_B7 m)7 RELCNFPHs;ND
+RNP3#FLF8b0FRMC4N;
+PHR3#8PED;R4
+@HR@g.::g4::vnRvQz_h6r4:Rj9v_vzQ4hr69:j;H
+NR83CHsVNsMN$NRlCv_vzQ;hR
+RNH3sbF0s8HRM"H"F;
+R.@@::4444:4:v(Rvmz_z4ar6.:49vRvzz_ma6r4:94.;H
+NR83CHsVNsMN$NRlCv_vzmRza;H
+NRF3bsH08sFR"k;0"
+@HR@4.:c::44cc:R)QmTN;
+HbR3F8s0H"sRH;M"
+@HR@4.:6::44.6:R;)7
+RNH3sbF0s8HRM"H"F;
+R.@@::4g4g:4:BnR1v)mpN;
+HbR3F8s0H"sRF"k0;R
+F@:@..4j:::.jn1RB)]mv;H
+NRF3bsH08sFR"k;0"
+@FR@..:4::4.64:R)B1q
+v;N3HRb0Fs8RHs"0Fk"F;
+R.@@::.d4d:.:BnR1)zqaN;
+HbR3F8s0H"sRF"k0;R
+F@:@..4c:::.c61RBB;aB
+RNH3sbF0s8HRk"F0
+";F@R@.6:.:.4:6R:6BQ1umN;
+HbR3F8s0H"sRF"k0;R
+b@:@44::44R:.fjj:RDVN#VCRNCD#R7th;R
+sfjj:ROlNEARQzbwRsRHlv_vzQ.hr9m
+S=zvv__QhO9r.
+jSQ=zvv_rQh.
+9;sjRf:ljRNROEQwAzRHbslvRvzh_Qr
+d9Svm=vQz_hr_OdS9
+Qvj=vQz_h9rd;R
+sfjj:ROlNEARQzbwRsRHlv_vzQchr9m
+S=zvv__QhO9rc
+jSQ=zvv_rQhc
+9;sjRf:ljRNROEQwAzRHbslvRvzh_Qr
+69Svm=vQz_hr_O6S9
+Qvj=vQz_h9r6;R
+sfjj:ROlNEARQzbwRsRHlv_vzQnhr9m
+S=zvv__QhO9rn
+jSQ=zvv_rQhn
+9;sjRf:ljRNROEQwAzRHbslvRvzh_Qr
+(9Svm=vQz_hr_O(S9
+Qvj=vQz_h9r(;R
+sfjj:ROlNEARQzbwRsRHlv_vzQ4hr.S9
+mv=vzh_Q_OO_r94.
+jSQ=zvv_rQh4;.9
+fsRjR:jlENORzQAwsRbHvlRvQz_hdr49m
+S=zvv__QhOr_O4
+d9S=Qjv_vzQ4hrd
+9;sjRf:ljRNROEQwAzRHbslvRvzh_Qr94c
+=Smv_vzQOh__4OrcS9
+Qvj=vQz_hcr49s;
+R:fjjNRlOQERARzwblsHRzvv_rQh4
+69Svm=vQz_h__OO6r49Q
+Sjv=vzh_Qr946;R
+sfjj:ROlNEARmzbwRsRHlv_vzmrza4
+.9Svm=vmz_z4ar.S9
+Qvj=vQz_h__OO.r49s;
+R:fjjNRlOmERARzwblsHRzvv_amzr94d
+=Smv_vzmrza4
+d9S=Qjv_vzQOh__4Ord
+9;sjRf:ljRNROEmwAzRHbslvRvzz_macr49m
+S=zvv_amzr94c
+jSQ=zvv__QhOr_O4;c9
+fsRjR:jlENORzmAwsRbHvlRvmz_z4ar6S9
+mv=vzz_ma6r49Q
+Sjv=vzh_Q_OO_r946;R
+sfjj:ROlNEARQzbwRsRHlQTm)
+=SmQTm)_SO
+QQj=m;)T
+fsRjR:jlENORzmAwsRbHBlR1v)mpm
+S=)B1m
+vpS=QjFob_CM_k.Oc_#lsFE__HOs;
+R:fjjNRlOmERARzwblsHR)B1m
+v]SBm=1v)m]Q
+SjM=k4O._#lsFE__HOs;
+R:fjjNRlOmERARzwblsHR)B1qSv
+m1=B)
+qvS=Qjv_vzQHh__4Or6
+9;sjRf:ljRNROEmwAzRHbsl1RBzaq)
+=SmBq1z)Sa
+Qtj=h
+7;sjRf:ljRNROEmwAzRHbsl1RBB
+aBSBm=1BBa
+jSQ=7th;R
+sfjj:ROlNEARmzbwRsRHlBQ1umm
+S=uB1QSm
+Qhj=_44U_jH__
+O;s4Rf6jj:ROlNEhRq7b.RsRHlknM._bO#HSF
+m_=h4
+U4S=QjFDb_0M_k4O4_#FbH
+4SQ=4h_U
+c;sjRf:ljRNROEq.h7RHbslMRk.On_#FbH34t_USc
+m_=h4
+UcS=Qjv_vzQOh_r
+c9S=Q4QTm)_
+H;sjRf:ljRNROEQRheblsHRzvv__QhH9rn
+=Smv_vzQHh__njr9Q
+Sjv=vzh_Q_nOr9s;
+R:fjjNRlOQERhbeRsRHlv_vzQHh_r
+69Svm=vQz_h__Hj9r6
+jSQ=zvv__QhO9r6;R
+sfjj:ROlNEhRQesRbHvlRvQz_hr_HdS9
+mv=vzh_Q_jH_r
+d9S=Qjv_vzQOh_r;d9
+fsRjR:jlENOReQhRHbslvRvzh_Q_.Hr9m
+S=zvv__QhHr_j.S9
+Qvj=vQz_hr_O.
+9;sjRf:ljRNROEQRheblsHRzvv__QhHcr49m
+S=zvv__QhHr_j4
+c9S=Qjv_vzQOh__4Orc
+9;sjRf:ljRNROEQRheblsHRzvv__QhHdr49m
+S=zvv__QhHr_j4
+d9S=Qjv_vzQOh__4Ord
+9;sjRf:ljRNROEq.h7RHbslMRk4O._#lsFEm
+S=4kM.#_OsEFl
+jSQ=_FbDk0_M_44OF#slSE
+QF4=bC_o_.kMc#_OsEFl_OH_;R
+sfjj:ROlNEhRq7b.RsRHlt4_4nm
+S=4h_4S(
+Qvj=vQz_h__Hjcr49Q
+S4v=vzh_Q_jH_r94d;R
+sfjj:ROlNEhRq7b.RsRHlt4_4Um
+S=_FbokC_M_.cOF#slSE
+Qvj=vQz_h__HO6r49Q
+S4_=h4;4(
+fsRjR:jlENOR7qh.sRbHtlR_g4(
+=SmFDb_0M_k4O4_#lsFEQ
+Sjv=vzh_Q_OH_r946
+4SQ=zvv__QhHr_j4;c9
+fsRjR:jlENOR7qh.sRbHtlR_
+cgShm=_
+64S=Qjv_vzQHh__djr9Q
+S4v=vzh_Q_jH_r;.9
+fsRjR:jlENOR7qh.sRbHtlR_
+6dShm=_
+6cS=Qjh4_6
+4SQ=zvv__QhHr_j6
+9;sjRf:ljRNROEq.h7RHbsl_Rt6S6
+m_=h6Sn
+Qhj=_
+6cS=Q4v_vzQHh__njr9s;
+R:fjjNRlOqERhR7.blsHR6t_(m
+S=_FbDk0_M_44OH#bFQ
+Sj_=h6Sn
+Qv4=vQz_h__Hj9r(;R
+sfjj:ROlNEhRQesRbHhlR_44U_SH
+m_=h4_U4H__jOQ
+Sj_=h4;U4
+fsRjR:jlENOReQhRHbslvRvzh_Q_4Hr6S9
+mv=vzh_Q_OH_r946
+jSQ=zvv__QhOr_O4;69
+fsRjR:jlENOReQhRHbslMRk4O._#lsFE
+_HSkm=M_4.OF#slHE__SO
+Qkj=M_4.OF#sl
+E;sjRf:ljRNROEQRheblsHR_FbokC_M_.cOF#slHE_
+=SmFob_CM_k.Oc_#lsFE__HOQ
+Sjb=F__oCkcM._sO#F;lE
+fsRjR:jlENOReQhRHbslmRQ)HT_
+=SmQTm)_SH
+QQj=m_)TOs;
+R:fjjNRlOQERhbeRsRHlv_vzQHh_r
+(9Svm=vQz_h__Hj9r(
+jSQ=zvv__QhO9r(;R
+bfjj:Rk0sCBReBBReB
+;
+
diff --git a/sw/cpld/address_decoder.srs b/sw/cpld/address_decoder.srs new file mode 100755 index 0000000..aaeb250 --- /dev/null +++ b/sw/cpld/address_decoder.srs @@ -0,0 +1,52 @@ +#
+#
+#
+# Created by Synplify VHDL Compiler version 5.3.0 from Synplicity, Inc.
+# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
+# Synthesis Netlist written on Thu Nov 23 11:54:34 2017
+#
+#
+#OPTIONS:"|-ram|-sm|-fid2|-sharing|on|-encrypt|-top|ADDRESS_DECODER|-ui|-lite|-lib|work"
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\bin\\c_vhdl.exe":944583556l
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\lib\\vhd\\location.map":975422018l
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\lib\\vhd\\std.vhd":927461368l
+#CUR:"C:\\_prossn\\cpld.nao\\address_decoder.vhd":1511438068l
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\lib\\vhd\\std1164.vhd":927461368l
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\lib\\vhd\\arith.vhd":941645104l
+#CUR:"C:\\ISPTOOLS\\SYNPBASE\\lib\\vhd\\unsigned.vhd":927461368l
+f "C:\ISPTOOLS\SYNPBASE\lib\vhd\std.vhd"; # file 0
+f "C:\_prossn\cpld.nao\address_decoder.vhd"; # file 1
+f "C:\ISPTOOLS\SYNPBASE\lib\vhd\std1164.vhd"; # file 2
+f "C:\ISPTOOLS\SYNPBASE\lib\vhd\arith.vhd"; # file 3
+f "C:\ISPTOOLS\SYNPBASE\lib\vhd\unsigned.vhd"; # file 4
+@E@MR@n4::n(::R.4I FsR7q7)1 1_B7 m)7 RELCNFPHs;ND
+RNP3PH#ER8D4H;
+R4@@:4g::ng:Rzvv_rQh4j6:9vRvzh_Qr:46j
+9;F@R@44:4:44:4R:(v_vzmrza446:.v9RvQz_h6r4:94.;R
+H@:@444c:::4ccmRQ)QTRm;)T
+@HR@44:6::44.6:RR)7)
+7;F@R@4g:4:44:gR:nBm1)vkpRMk4_M_.cOF#sl
+E;F@R@4j:.:.4:jR:nBm1)vO]R#lsFEF;
+R4@@::.444:.:B6R1v)qR4kM_kll_rHM4;69
+@FR@.4:d::4.nd:RzB1qR)aBq1z)
+a;F@R@4c:.:.4:cR:6Ba1BB1RBB;aB
+@FR@.4:6::4.66:RuB1QOmR#FbH;R
+b@:@4g::4gR:nHRMPk_M4l_lkH4Mr6k9RMl4_lHk_M6r49vRvzh_Qr946;R
+b@:@444c:::4ccMRHPMRk4F_HskJRMH4_FRsJQTm);R
+b@:@j4::44R:.0CskRk0sCsR0k
+C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
+@bR@4j::44::L.RkBVR1BBaRBB1aVBRNCD#;R
+b@:@j4::44R:.LRkVBq1z)BaR1)zqaNRVD;#C
+@bR@.d:64.:(6:...:6RRD0Fob_CM_k.Oc_#FbHR_FbokC_M_.cOH#bFvRvzh_Qrj(:9NRVD,#CV#NDCN,VD,#C0Csk,DVN#VC,NCD#,DVN#VC,NCD#;R
+b@:@d.:(n4.(:(6n:40RDR_FbDk0_M_44OH#bFbRF__D0k4M4_bO#HvFRvQz_h:r(jV9RNCD#,DVN#VC,NCD#,k0sCN,VD,#C0Csk,DVN#VC,NCD#;R
+b@:@d.:6.4.(:66.:.MRHPMRk4M_k.Oc_#FbHR4kM_.kMc#_ObRHFFob_CM_k.Oc_#FbH;R
+b@:@d.:6.4.(:66.:.0RDR_FbokC_M_.cOF#slFERbC_o_.kMc#_OsEFlRzvv_rQh4j6:9NRVD,#CV#NDCs,0kVC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#;R
+b@:@d.:(n4.(:(6n:40RDR_FbDk0_M_44OF#slFERb0_D_4kM4#_OsEFlRzvv_rQh4j6:9NRVD,#C0Csk,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#;R
+b@:@d.:6.4.(:66.:.MRHPMRk4M_k.Oc_#lsFEMRk4M_k.Oc_#lsFEbRF__oCkcM._sO#F;lE
+@bR@c4:64:.::c6UN6RMR8PknM._bO#HkFRM_.nOH#bFbRF__D0k4M4_bO#HkFRMk4_M_.cOH#bFR
+RRMRk4F_Hs
+J;b@R@46:c:c(:6R:UHRMPOH#bF#RObRHFknM._bO#H
+F;b@R@4d:6::..6nd:6MRN8kPRM_4.OF#slkERM_4.OF#slFERb0_D_4kM4#_OsEFlR4kM_.kMc#_OsEFl;R
+b@:@46Ud:::6dgMRHP#ROsEFlRsO#FRlEk.M4_sO#F;lE
+
+C;
diff --git a/sw/cpld/address_decoder.sym b/sw/cpld/address_decoder.sym Binary files differnew file mode 100755 index 0000000..15805d3 --- /dev/null +++ b/sw/cpld/address_decoder.sym diff --git a/sw/cpld/address_decoder.syn b/sw/cpld/address_decoder.syn new file mode 100755 index 0000000..414a0b4 --- /dev/null +++ b/sw/cpld/address_decoder.syn @@ -0,0 +1,8 @@ +JDF B
+// Created by Version 8.3
+PROJECT Untitled
+DESIGN address_decoder Normal
+DEVKIT M4-32/32-15JC
+ENTRY Schematic/VHDL
+MODULE address_decoder.vhd
+MODSTYLE ADDRESS_DECODER Normal
diff --git a/sw/cpld/address_decoder.tal b/sw/cpld/address_decoder.tal new file mode 100755 index 0000000..434ebe5 --- /dev/null +++ b/sw/cpld/address_decoder.tal @@ -0,0 +1,42 @@ +
+
+Design Name = address_decoder.tt4
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+*******************
+* TIMING ANALYSIS *
+*******************
+
+Timing Analysis KEY:
+One unit of delay time is equivalent to one pass
+ through the Central Switch Matrix.
+.. Delay ( in this column ) not applicable to the indicated signal.
+TSU, Set-Up Time ( 0 for input-paired signals ),
+ represents the number of switch matrix passes between
+ an input pin and a register setup before clock.
+ TSU is reported on the register.
+TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
+ represents the number of switch matrix passes between
+ a clocked register and an output pin.
+ TCO is reported on the register.
+TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
+ represents the number of switch matrix passes between
+ an input pin and an output pin.
+ TPD is reported on the output pin.
+TCR, Clocked Output-to-Register Time,
+ represents the number of switch matrix passes between
+ a clocked register and the register it drives ( before clock ).
+ TCR is reported on the driving register.
+
+ TSU TCO TPD TCR
+ #passes #passes #passes #passes
+SIGNAL NAME min max min max min max min max
+ MMU_OUT_15_ .. .. .. .. 1 1 .. ..
+ CSROML .. .. .. .. 1 1 .. ..
+ CSROMH .. .. .. .. 1 1 .. ..
+ MMU_OUT_14_ .. .. .. .. 1 1 .. ..
+ CSRAM .. .. .. .. 1 1 .. ..
+ MMU_OUT_13_ .. .. .. .. 1 1 .. ..
+ MMU_OUT_12_ .. .. .. .. 1 1 .. ..
+ CSPIO .. .. .. .. 1 1 .. ..
\ No newline at end of file diff --git a/sw/cpld/address_decoder.tc_ b/sw/cpld/address_decoder.tc_ new file mode 100755 index 0000000..0054dc8 --- /dev/null +++ b/sw/cpld/address_decoder.tc_ @@ -0,0 +1,37 @@ +#-- Synplicity, Inc.
+#-- Synplify version 5.3.2
+#-- Project file C:\_prossn\cpld.nao\address_decoder.tc_
+#-- Written on Thu Nov 23 11:54:34 2017
+
+#device options
+set_option -technology mach
+set_option -part MACH111
+
+#add_file options
+add_file -vhdl -lib work "address_decoder.vhd"
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler false
+set_option -resource_sharing true
+
+#map options
+set_option -frequency 0.000
+set_option -fanin_limit 20
+set_option -max_terms_per_macrocell 16
+set_option -map_logic false
+set_option -area_delay_percent 0
+set_option -top_module ADDRESS_DECODER
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint true
+
+#MTI Cross Probe options
+set_option -mti_root ""
+
+#set result format/file last
+project -result_file "address_decoder.edi"
diff --git a/sw/cpld/address_decoder.tlg b/sw/cpld/address_decoder.tlg new file mode 100755 index 0000000..b1a2595 --- /dev/null +++ b/sw/cpld/address_decoder.tlg @@ -0,0 +1,3 @@ +Synthesizing work.address_decoder.behavioral
+Post processing for work.address_decoder.behavioral
+@W:"C:\_prossn\cpld.nao\address_decoder.vhd":15:1:15:2|Input rd is unused
diff --git a/sw/cpld/address_decoder.trp b/sw/cpld/address_decoder.trp new file mode 100755 index 0000000..2c329e3 --- /dev/null +++ b/sw/cpld/address_decoder.trp @@ -0,0 +1,75 @@ +
+Timing Report for STAMP
+
+// Project = address_decoder
+// Family = M4
+// Device = M4-32/32
+// Speed = -15
+// Voltage = 5.0
+// Operating Condition = COM
+// Data sheet version = 1.01
+
+// Pass Bidirection = OFF
+// Pass S/R = OFF
+// Pass Latch = OFF
+// Pass Clock = OFF
+// Maximum Paths = 20
+// T_SU Endpoints D/T inputs = ON
+// T_SU Endpoints CE inputs = OFF
+// T_SU Endpoints S/R inputs = OFF
+
+
+Section IO
+ //DESTINATION NODES;
+ CSCTC [out]
+ CSPIO [out]
+ CSRAM [out]
+ CSROMH [out]
+ CSROML [out]
+ CSUART [out]
+ MMU_OUT[12] [out]
+ MMU_OUT[13] [out]
+ MMU_OUT[14] [out]
+ MMU_OUT[15] [out]
+
+ //SOURCE NODES;
+ MMU_IN[2] [in]
+ MMU_IN[3] [in]
+ MMU_IN[4] [in]
+ MMU_IN[5] [in]
+ MMU_IN[6] [in]
+ MMU_IN[7] [in]
+ MMU_IN[8] [in]
+ MMU_IN[9] [in]
+ MMU_IN[10] [in]
+ MMU_IN[11] [in]
+ MMU_IN[12] [in]
+ MMU_IN[13] [in]
+ MMU_IN[14] [in]
+ MMU_IN[15] [in]
+
+
+Section tPD
+
+ Delay Location(From => To) Source Destination
+ ===== ==================== ====== ===========
+ 15.0 p7 => p27 MMU_IN[2] CSUART
+ 15.0 p6 => p27 MMU_IN[3] CSUART
+ 15.0 p5 => p27 MMU_IN[4] CSUART
+ 15.0 p4 => p27 MMU_IN[5] CSUART
+ 15.0 p3 => p27 MMU_IN[6] CSUART
+ 15.0 p2 => p27 MMU_IN[7] CSUART
+ 15.0 p14 => p28 MMU_IN[8] CSCTC
+ 15.0 p14 => p29 MMU_IN[8] CSPIO
+ 15.0 p14 => p27 MMU_IN[8] CSUART
+ 15.0 p15 => p28 MMU_IN[9] CSCTC
+ 15.0 p15 => p29 MMU_IN[9] CSPIO
+ 15.0 p15 => p27 MMU_IN[9] CSUART
+ 15.0 p16 => p28 MMU_IN[10] CSCTC
+ 15.0 p16 => p29 MMU_IN[10] CSPIO
+ 15.0 p16 => p27 MMU_IN[10] CSUART
+ 15.0 p17 => p28 MMU_IN[11] CSCTC
+ 15.0 p17 => p29 MMU_IN[11] CSPIO
+ 15.0 p17 => p27 MMU_IN[11] CSUART
+ 15.0 p18 => p28 MMU_IN[12] CSCTC
+ 15.0 p18 => p29 MMU_IN[12] CSPIO
diff --git a/sw/cpld/address_decoder.tt2 b/sw/cpld/address_decoder.tt2 new file mode 100755 index 0000000..9c670f0 --- /dev/null +++ b/sw/cpld/address_decoder.tt2 @@ -0,0 +1,33 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE address_decoder
+#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
+.type fr
+.i 11
+.o 10
+.ilb MMU_IN_15_ IORQ MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_7_ MMU_IN_6_ MMU_IN_5_ MMU_IN_4_ MMU_IN_3_ MMU_IN_2_
+.ob MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ MMU_OUT_13_ MMU_OUT_12_
+.p 22
+1---------- 111~~~~~~~
+0---------- ~~~1~~~~~~
+-1--------- ~~~~~~1~~~
+--1-------- ~11~~~~1~~
+---1------- ~1~~~~~~1~
+---0------- ~~1~~~~~~~
+----1------ ~~~~~~~~~1
+-----1----- ~~~~~~1~~~
+------1---- ~~~~~~1~~~
+-------1--- ~~~~~~1~~~
+--------0-- ~~~~~~1~~~
+---------1- ~~~~~~1~~~
+----------1 ~~~~~~1~~~
+----------- ~~~~00~~~~
+1---------- ~~~0~~~~~~
+0---------- 0~~~~~~~~~
+--0-------- ~~~~~~~0~~
+0-01------- ~~0~~~~~~~
+---0------- ~~~~~~~~0~
+0-00------- ~0~~~~~~~~
+----0------ ~~~~~~~~~0
+-0---000100 ~~~~~~0~~~
+.end
diff --git a/sw/cpld/address_decoder.tt3 b/sw/cpld/address_decoder.tt3 new file mode 100755 index 0000000..7df2081 --- /dev/null +++ b/sw/cpld/address_decoder.tt3 @@ -0,0 +1,33 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE address_decoder
+#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_ MMU_IN_3_ IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
+.type fr
+.i 11
+.o 10
+.ilb MMU_IN_15_ IORQ MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_7_ MMU_IN_6_ MMU_IN_5_ MMU_IN_4_ MMU_IN_3_ MMU_IN_2_
+.ob MMU_OUT_15_ CSROML CSROMH CSRAM CSUART CSCTC CSPIO MMU_OUT_14_ MMU_OUT_13_ MMU_OUT_12_
+.p 22
+1---------- 111~~~~~~~
+0---------- ~~~1~~~~~~
+-1--------- ~~~~~~1~~~
+--1-------- ~11~~~~1~~
+---1------- ~1~~~~~~1~
+---0------- ~~1~~~~~~~
+----1------ ~~~~~~~~~1
+-----1----- ~~~~~~1~~~
+------1---- ~~~~~~1~~~
+-------1--- ~~~~~~1~~~
+--------0-- ~~~~~~1~~~
+---------1- ~~~~~~1~~~
+----------1 ~~~~~~1~~~
+----------- ~~~~00~~~~
+1---------- ~~~0~~~~~~
+0---------- 0~~~~~~~~~
+--0-------- ~~~~~~~0~~
+0-01------- ~~0~~~~~~~
+---0------- ~~~~~~~~0~
+0-00------- ~0~~~~~~~~
+----0------ ~~~~~~~~~0
+-0---000100 ~~~~~~0~~~
+.end
diff --git a/sw/cpld/address_decoder.tt4 b/sw/cpld/address_decoder.tt4 new file mode 100755 index 0000000..4a58b90 --- /dev/null +++ b/sw/cpld/address_decoder.tt4 @@ -0,0 +1,25 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE ADDRESS_DECODER
+#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_
+ MMU_IN_3_ IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART
+ MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
+.type f
+.i 11
+.o 10
+.ilb MMU_IN_15_ IORQ MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_7_ MMU_IN_6_
+ MMU_IN_5_ MMU_IN_4_ MMU_IN_3_ MMU_IN_2_
+.ob MMU_OUT_15_ CSROML% CSROMH% MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_
+ CSCTC CSPIO%
+.phase 1111111111
+.p 9
+1---------- 1000000000
+0-00------- 0100000000
+0-01------- 0010000000
+--1-------- 0001000000
+0---------- 0000100000
+---1------- 0000010000
+----------- 0000000000
+----1------ 0000000100
+-0---000100 0000000001
+.end
diff --git a/sw/cpld/address_decoder.tte b/sw/cpld/address_decoder.tte new file mode 100755 index 0000000..94da533 --- /dev/null +++ b/sw/cpld/address_decoder.tte @@ -0,0 +1,25 @@ +#$ TOOL ispDesignEXPERT 8.3.02.12
+#$ DATE Thu Nov 23 11:54:43 2017
+#$ MODULE ADDRESS_DECODER
+#$ PINS 21 MMU_IN_7_ MMU_IN_6_ MMU_IN_15_ MMU_IN_5_ MMU_IN_4_ MMU_OUT_15_
+ MMU_IN_3_ IORQ MMU_IN_2_ CSROML CSROMH MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART
+ MMU_OUT_12_ CSCTC CSPIO MMU_IN_14_ MMU_IN_13_ MMU_IN_12_
+.type f
+.i 11
+.o 10
+.ilb MMU_IN_15_ IORQ MMU_IN_14_ MMU_IN_13_ MMU_IN_12_ MMU_IN_7_ MMU_IN_6_
+ MMU_IN_5_ MMU_IN_4_ MMU_IN_3_ MMU_IN_2_
+.ob MMU_OUT_15_ CSROML- CSROMH- MMU_OUT_14_ CSRAM MMU_OUT_13_ CSUART MMU_OUT_12_
+ CSCTC CSPIO-
+.phase 1111111111
+.p 9
+1---------- 1000000000
+0-00------- 0100000000
+0-01------- 0010000000
+--1-------- 0001000000
+0---------- 0000100000
+---1------- 0000010000
+----------- 0000000000
+----1------ 0000000100
+-0---000100 0000000001
+.end
diff --git a/sw/cpld/address_decoder.vci b/sw/cpld/address_decoder.vci new file mode 100755 index 0000000..2582a78 --- /dev/null +++ b/sw/cpld/address_decoder.vci @@ -0,0 +1,82 @@ +
+[Device]
+Family = M4;
+PartNumber = M4-32/32-15JC;
+Package = 44PLCC;
+PartType = M4-32/32;
+Speed = -15;
+Operating_condition = COM;
+Status = Production;
+
+[Revision]
+Parent = m4.vci;
+Design = ;
+DATE = 09/25/2017;
+TIME = 16:10:34;
+
+[IGNORE ASSIGNMENTS]
+
+[CLEAR ASSIGNMENTS]
+
+[BACKANNOTATE ASSIGNMENTS]
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+[OPTIMIZATION OPTIONS]
+
+[FITTER GLOBAL OPTIONS]
+
+[LOCATION ASSIGNMENT]
+layer = OFF;
+CSROML = Output, 24, B, -;
+CSROMH = Output, 25, B, -;
+CSRAM = Output, 26, B, -;
+CSUART = Output, 27, B, -;
+CSCTC = Output, 28, B, -;
+CSPIO = Output, 29, B, -;
+MMU_IN_0_ = Input, 9, A, -;
+MMU_IN_1_ = Input, 8, A, -;
+MMU_IN_2_ = Input, 7, A, -;
+MMU_IN_3_ = Input, 6, A, -;
+MMU_IN_4_ = Input, 5, A, -;
+MMU_IN_5_ = Input, 4, A, -;
+MMU_IN_6_ = Input, 3, A, -;
+MMU_IN_7_ = Input, 2, A, -;
+MMU_IN_8_ = Input, 14, A, -;
+MMU_IN_9_ = Input, 15, A, -;
+MMU_IN_10_ = Input, 16, A, -;
+MMU_IN_11_ = Input, 17, A, -;
+MMU_IN_12_ = Input, 18, A, -;
+MMU_IN_13_ = Input, 19, A, -;
+MMU_IN_14_ = Input, 20, A, -;
+MMU_IN_15_ = Input, 21, A, -;
+MMU_OUT_12_ = Output, 39, B, -;
+MMU_OUT_13_ = Output, 38, B, -;
+MMU_OUT_14_ = Output, 37, B, -;
+MMU_OUT_15_ = Output, 36, B, -;
+IORQ = Input, 30, B, -;
+
+[GROUP ASSIGNMENT]
+layer = OFF;
+
+[SPACE RESERVATIONS]
+layer = OFF;
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[FITTER REPORT FORMAT]
+
+[POWER]
+
+[SOURCE CONSTRAINT OPTION]
+
+[HARDWARE DEVICE OPTIONS]
+
+[PULL]
+
+[OPENDRAIN]
+
+[Timing Analyzer]
+
+[Backannotate Netlist]
diff --git a/sw/cpld/address_decoder.vcl b/sw/cpld/address_decoder.vcl new file mode 100755 index 0000000..6befbd2 --- /dev/null +++ b/sw/cpld/address_decoder.vcl @@ -0,0 +1,136 @@ +[DEVICE]
+
+Family = M4;
+PartType = M4-32/32;
+Package = 44PLCC;
+PartNumber = M4-32/32-15JC;
+Speed = -15;
+Operating_condition = COM;
+EN_Segment = NO;
+Pin_MC_1to1 = NO;
+Voltage = 5.0;
+
+[REVISION]
+
+RCS = "$Revision: 1.24 $";
+Parent = m4.vci;
+SDS_file = m4.sds;
+Design = address_decoder.tt4;
+Rev = 0.01;
+DATE = 11/23/17;
+TIME = 11:55:45;
+Type = TT2;
+Pre_Fit_Time = 1;
+Source_Format = ABEL_Schematic;
+
+[IGNORE ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[CLEAR ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[BACKANNOTATE NETLIST]
+
+Netlist = VHDL;
+Delay_File = SDF;
+Generic_VCC = ;
+Generic_GND = ;
+
+[BACKANNOTATE ASSIGNMENTS]
+
+Pin_Assignment = NO;
+Pin_Block = NO;
+Pin_Macrocell_Block = NO;
+Routing = NO;
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+Balanced_Partitioning = YES;
+Spread_Placement = YES;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_Inter_Seg_Percent = 100;
+Max_Seg_In_Percent = 100;
+Max_Blk_In_Percent = 100;
+
+[FITTER REPORT FORMAT]
+
+Fitter_Options = YES;
+Pinout_Diagram = NO;
+Pinout_Listing = YES;
+Detailed_Block_Segment_Summary = YES;
+Input_Signal_List = YES;
+Output_Signal_List = YES;
+Bidir_Signal_List = YES;
+Node_Signal_List = YES;
+Signal_Fanout_List = YES;
+Block_Segment_Fanin_List = YES;
+Prefit_Eqn = YES;
+Postfit_Eqn = YES;
+Page_Break = YES;
+
+[OPTIMIZATION OPTIONS]
+
+Logic_Reduction = YES;
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+XOR_Synthesis = YES;
+Node_Collapse = Yes;
+DT_Synthesis = Yes;
+
+[FITTER GLOBAL OPTIONS]
+
+Run_Time = 0;
+Set_Reset_Dont_Care = NO;
+In_Reg_Optimize = YES;
+Clock_Optimize = NO;
+Conf_Unused_IOs = OUT_LOW;
+
+[POWER]
+
+[HARDWARE DEVICE OPTIONS]
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[LOCATION ASSIGNMENT]
+
+Layer = OFF
+MMU_OUT_12_ = OUTPUT,39,1,-;
+MMU_OUT_13_ = OUTPUT,38,1,-;
+MMU_OUT_14_ = OUTPUT,37,1,-;
+MMU_OUT_15_ = OUTPUT,36,1,-;
+CSPIO = OUTPUT,29,1,-;
+CSCTC = OUTPUT,28,1,-;
+CSUART = OUTPUT,27,1,-;
+CSRAM = OUTPUT,26,1,-;
+CSROMH = OUTPUT,25,1,-;
+CSROML = OUTPUT,24,1,-;
diff --git a/sw/cpld/address_decoder.vco b/sw/cpld/address_decoder.vco new file mode 100755 index 0000000..229e06f --- /dev/null +++ b/sw/cpld/address_decoder.vco @@ -0,0 +1,147 @@ +[DEVICE]
+
+Family = M4;
+PartType = M4-32/32;
+Package = 44PLCC;
+PartNumber = M4-32/32-15JC;
+Speed = -15;
+Operating_condition = COM;
+EN_Segment = NO;
+Pin_MC_1to1 = NO;
+Voltage = 5.0;
+
+[REVISION]
+
+RCS = "$Revision: 1.24 $";
+Parent = m4.vci;
+SDS_file = m4.sds;
+Design = address_decoder.tt4;
+Rev = 0.01;
+DATE = 11/23/17;
+TIME = 11:55:45;
+Type = TT2;
+Pre_Fit_Time = 1;
+Source_Format = ABEL_Schematic;
+
+[IGNORE ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[CLEAR ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[BACKANNOTATE NETLIST]
+
+Netlist = VHDL;
+Delay_File = SDF;
+Generic_VCC = ;
+Generic_GND = ;
+
+[BACKANNOTATE ASSIGNMENTS]
+
+Pin_Assignment = NO;
+Pin_Block = NO;
+Pin_Macrocell_Block = NO;
+Routing = NO;
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+Balanced_Partitioning = YES;
+Spread_Placement = YES;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_Inter_Seg_Percent = 100;
+Max_Seg_In_Percent = 100;
+Max_Blk_In_Percent = 100;
+
+[FITTER REPORT FORMAT]
+
+Fitter_Options = YES;
+Pinout_Diagram = NO;
+Pinout_Listing = YES;
+Detailed_Block_Segment_Summary = YES;
+Input_Signal_List = YES;
+Output_Signal_List = YES;
+Bidir_Signal_List = YES;
+Node_Signal_List = YES;
+Signal_Fanout_List = YES;
+Block_Segment_Fanin_List = YES;
+Prefit_Eqn = YES;
+Postfit_Eqn = YES;
+Page_Break = YES;
+
+[OPTIMIZATION OPTIONS]
+
+Logic_Reduction = YES;
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+XOR_Synthesis = YES;
+Node_Collapse = Yes;
+DT_Synthesis = Yes;
+
+[FITTER GLOBAL OPTIONS]
+
+Run_Time = 0;
+Set_Reset_Dont_Care = NO;
+In_Reg_Optimize = YES;
+Clock_Optimize = NO;
+Conf_Unused_IOs = OUT_LOW;
+
+[POWER]
+
+[HARDWARE DEVICE OPTIONS]
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[LOCATION ASSIGNMENT]
+
+Layer = OFF;
+MMU_IN_7_ = INPUT,2, A,-;
+MMU_IN_6_ = INPUT,3, A,-;
+MMU_IN_15_ = INPUT,21, A,-;
+MMU_IN_5_ = INPUT,4, A,-;
+MMU_IN_4_ = INPUT,5, A,-;
+MMU_OUT_15_ = OUTPUT,36, B,-;
+MMU_IN_3_ = INPUT,6, A,-;
+IORQ = INPUT,30, B,-;
+MMU_IN_2_ = INPUT,7, A,-;
+CSROML = OUTPUT,24, B,-;
+CSROMH = OUTPUT,25, B,-;
+MMU_OUT_14_ = OUTPUT,37, B,-;
+CSRAM = OUTPUT,26, B,-;
+MMU_OUT_13_ = OUTPUT,38, B,-;
+CSUART = OUTPUT,27, B,-;
+MMU_OUT_12_ = OUTPUT,39, B,-;
+CSCTC = OUTPUT,28, B,-;
+CSPIO = OUTPUT,29, B,-;
+MMU_IN_14_ = INPUT,20, A,-;
+MMU_IN_13_ = INPUT,19, A,-;
+MMU_IN_12_ = INPUT,18, A,-;
diff --git a/sw/cpld/address_decoder.vct b/sw/cpld/address_decoder.vct new file mode 100755 index 0000000..2582a78 --- /dev/null +++ b/sw/cpld/address_decoder.vct @@ -0,0 +1,82 @@ +
+[Device]
+Family = M4;
+PartNumber = M4-32/32-15JC;
+Package = 44PLCC;
+PartType = M4-32/32;
+Speed = -15;
+Operating_condition = COM;
+Status = Production;
+
+[Revision]
+Parent = m4.vci;
+Design = ;
+DATE = 09/25/2017;
+TIME = 16:10:34;
+
+[IGNORE ASSIGNMENTS]
+
+[CLEAR ASSIGNMENTS]
+
+[BACKANNOTATE ASSIGNMENTS]
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+[OPTIMIZATION OPTIONS]
+
+[FITTER GLOBAL OPTIONS]
+
+[LOCATION ASSIGNMENT]
+layer = OFF;
+CSROML = Output, 24, B, -;
+CSROMH = Output, 25, B, -;
+CSRAM = Output, 26, B, -;
+CSUART = Output, 27, B, -;
+CSCTC = Output, 28, B, -;
+CSPIO = Output, 29, B, -;
+MMU_IN_0_ = Input, 9, A, -;
+MMU_IN_1_ = Input, 8, A, -;
+MMU_IN_2_ = Input, 7, A, -;
+MMU_IN_3_ = Input, 6, A, -;
+MMU_IN_4_ = Input, 5, A, -;
+MMU_IN_5_ = Input, 4, A, -;
+MMU_IN_6_ = Input, 3, A, -;
+MMU_IN_7_ = Input, 2, A, -;
+MMU_IN_8_ = Input, 14, A, -;
+MMU_IN_9_ = Input, 15, A, -;
+MMU_IN_10_ = Input, 16, A, -;
+MMU_IN_11_ = Input, 17, A, -;
+MMU_IN_12_ = Input, 18, A, -;
+MMU_IN_13_ = Input, 19, A, -;
+MMU_IN_14_ = Input, 20, A, -;
+MMU_IN_15_ = Input, 21, A, -;
+MMU_OUT_12_ = Output, 39, B, -;
+MMU_OUT_13_ = Output, 38, B, -;
+MMU_OUT_14_ = Output, 37, B, -;
+MMU_OUT_15_ = Output, 36, B, -;
+IORQ = Input, 30, B, -;
+
+[GROUP ASSIGNMENT]
+layer = OFF;
+
+[SPACE RESERVATIONS]
+layer = OFF;
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[FITTER REPORT FORMAT]
+
+[POWER]
+
+[SOURCE CONSTRAINT OPTION]
+
+[HARDWARE DEVICE OPTIONS]
+
+[PULL]
+
+[OPENDRAIN]
+
+[Timing Analyzer]
+
+[Backannotate Netlist]
diff --git a/sw/cpld/address_decoder.vhd b/sw/cpld/address_decoder.vhd index 2c80f86..5f32637 100644..100755 --- a/sw/cpld/address_decoder.vhd +++ b/sw/cpld/address_decoder.vhd @@ -1,37 +1,59 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity ADDRESS_DECODER is - -port( - -- address input - PA: in unsigned(15 downto 0); - - -- chip selects output - -- memory - CSROMH: out std_logic; - CSROML: out std_logic; - CSRAM : out std_logic; - -- io chips - CSUART: out std_logic; - CSCTC : out std_logic; - CSPIO : out std_logic -); - -end; - -architecture Behavioral of ADDRESS_DECODER is -begin - -- memory - CSROMH <= 0 when ((PA >= x"0000") and (PA < x"2000")); - CSROML <= 0 when ((PA >= x"4000") and (PA < x"4000")); - CSRAM <= 0 when (PA >= x"D000"); - -- io chips - CSUART <= 0 when ((PA >= x"4000") and (PA < x"4008")); - -- CSCTC - -- CSPIO - -end Behavioral; - +library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity ADDRESS_DECODER is
+port(
+ -- address input
+ MMU_IN: in std_logic_vector(15 downto 0);
+ -- address output
+ MMU_OUT: out std_logic_vector(15 downto 12);
+
+ -- other signals
+ IORQ: in std_logic;
+ RD: in std_logic;
+
+ -- chip selects output
+ -- memory
+ CSROML: out std_logic;
+ CSROMH: out std_logic;
+ CSRAM : out std_logic;
+ -- io chips
+ CSUART: out std_logic;
+ CSCTC : out std_logic;
+ CSPIO : out std_logic
+);
+end;
+
+architecture Behavioral of ADDRESS_DECODER is
+ signal ADDR_IN_LOW : unsigned (7 downto 0);
+ signal ADDR_IN_HIGH : unsigned (7 downto 0);
+ signal ADDR_IN : unsigned (15 downto 0);
+begin
+ -- PAGE TABLE (disabled)
+ MMU_OUT <= MMU_IN(15 downto 12);
+
+ -- ENABLE SIGNALS
+ ADDR_IN_LOW <= unsigned(MMU_IN(7 downto 0));
+ ADDR_IN_HIGH <= unsigned(MMU_IN(15 downto 8));
+ ADDR_IN <= unsigned(MMU_IN);
+
+ -- io chips:
+ ---- region 0x0000 - 0x00FF ----
+
+ CSPIO <= '0' when ((ADDR_IN_LOW >= 16#10#) and (ADDR_IN_LOW < 16#14#) and (IORQ = '0')) else '1';
+ -- CSPIO <= '0' when ((ADDR_IN >= 16#0010#) and (ADDR_IN < 16#0014#)) else '1';
+ -- CSCTC <= '0' when ((ADDR_IN >= 16#4100#) and (ADDR_IN < 16#4200#)) else '1'; -- test address range
+ --CSUART <= '0' when ((ADDR_IN >= 16#4200#) and (ADDR_IN < 16#4300#)) else '1'; -- test address range
+
+ -- read only memory:
+ ---- region 0x0000 - 0x4000 ----
+ CSROML <= '0' when ((ADDR_IN >= 16#0000#) and (ADDR_IN < 16#2000#)) else '1';
+ CSROMH <= '0' when ((ADDR_IN >= 16#2000#) and (ADDR_IN < 16#4000#)) else '1';
+
+ -- random access memory:
+ ---- region 0x8000 - 0xFFFF ----
+ CSRAM <= '0' when (ADDR_IN >= 16#8000#) else '1';
+end Behavioral;
+
diff --git a/sw/cpld/address_decoder.vhm b/sw/cpld/address_decoder.vhm new file mode 100755 index 0000000..937f6e2 --- /dev/null +++ b/sw/cpld/address_decoder.vhm @@ -0,0 +1,288 @@ +--
+-- Written by Synplicity
+-- Thu Nov 23 11:54:35 2017
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library synplify;
+use synplify.components.all;
+entity AND2 is
+port(
+ O : out std_logic;
+ I0 : in std_logic;
+ I1 : in std_logic);
+end AND2;
+
+architecture beh of AND2 is
+ signal NN_1 : std_logic ;
+ signal NN_2 : std_logic ;
+begin
+ NN_1 <= '1';
+ NN_2 <= '0';
+ O <= I0 and I1 after 100 ps;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library synplify;
+use synplify.components.all;
+entity IBUF is
+port(
+ O : out std_logic;
+ I0 : in std_logic);
+end IBUF;
+
+architecture beh of IBUF is
+ signal NN_1 : std_logic ;
+ signal NN_2 : std_logic ;
+begin
+ O <= I0;
+ NN_1 <= '1';
+ NN_2 <= '0';
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library synplify;
+use synplify.components.all;
+entity INV is
+port(
+ O : out std_logic;
+ I0 : in std_logic);
+end INV;
+
+architecture beh of INV is
+ signal NN_1 : std_logic ;
+ signal NN_2 : std_logic ;
+begin
+ O <= not I0;
+ NN_1 <= '1';
+ NN_2 <= '0';
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library synplify;
+use synplify.components.all;
+entity OBUF is
+port(
+ O : out std_logic;
+ I0 : in std_logic);
+end OBUF;
+
+architecture beh of OBUF is
+ signal NN_1 : std_logic ;
+ signal NN_2 : std_logic ;
+begin
+ O <= I0;
+ NN_1 <= '1';
+ NN_2 <= '0';
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library synplify;
+use synplify.components.all;
+entity ADDRESS_DECODER is
+port(
+ MMU_IN : in std_logic_vector(15 downto 0);
+ MMU_OUT : out std_logic_vector(15 downto 12);
+ IORQ : in std_logic;
+ RD : in std_logic;
+ CSROML : out std_logic;
+ CSROMH : out std_logic;
+ CSRAM : out std_logic;
+ CSUART : out std_logic;
+ CSCTC : out std_logic;
+ CSPIO : out std_logic);
+end ADDRESS_DECODER;
+
+architecture beh of ADDRESS_DECODER is
+ signal MMU_IN_I_0 : std_logic_vector(14 downto 2);
+ signal MMU_IN_C : std_logic_vector(7 downto 2);
+ signal MMU_IN_C_C : std_logic_vector(15 downto 12);
+ signal MMU_IN_I_C : std_logic_vector(15 to 15);
+ signal OP_GE_UN24_CSROMH : std_logic ;
+ signal OP_LT_UN11_CSROMH : std_logic ;
+ signal UN12_CSROMH : std_logic ;
+ signal N_117 : std_logic ;
+ signal N_181 : std_logic ;
+ signal OP_LT_UN11_CSPIO : std_logic ;
+ signal N_56 : std_logic ;
+ signal N_54 : std_logic ;
+ signal N_51 : std_logic ;
+ signal IORQ_I : std_logic ;
+ signal IORQ_C : std_logic ;
+ signal OP_GE_UN24_CSROMH_I_C : std_logic ;
+ signal UN12_CSROMH_I_C : std_logic ;
+ signal N_181_I_0_C : std_logic ;
+ signal GND : std_logic ;
+ signal N_184 : std_logic ;
+ signal VCC : std_logic ;
+ component IBUF
+ port(O : out std_logic;
+ I0 : in std_logic );
+ end component;
+ component OBUF
+ port(O : out std_logic;
+ I0 : in std_logic );
+ end component;
+ component AND2
+ port(O : out std_logic;
+ I0 : in std_logic;
+ I1 : in std_logic );
+ end component;
+ component INV
+ port(O : out std_logic;
+ I0 : in std_logic );
+ end component;
+begin
+ GND <= '0';
+ \II_MMU_IN[2]\: IBUF port map (
+ O => MMU_IN_C(2),
+ I0 => MMU_IN(2));
+ \II_MMU_IN[3]\: IBUF port map (
+ O => MMU_IN_C(3),
+ I0 => MMU_IN(3));
+ \II_MMU_IN[4]\: IBUF port map (
+ O => MMU_IN_C(4),
+ I0 => MMU_IN(4));
+ \II_MMU_IN[5]\: IBUF port map (
+ O => MMU_IN_C(5),
+ I0 => MMU_IN(5));
+ \II_MMU_IN[6]\: IBUF port map (
+ O => MMU_IN_C(6),
+ I0 => MMU_IN(6));
+ \II_MMU_IN[7]\: IBUF port map (
+ O => MMU_IN_C(7),
+ I0 => MMU_IN(7));
+ \II_MMU_IN[12]\: IBUF port map (
+ O => MMU_IN_C_C(12),
+ I0 => MMU_IN(12));
+ \II_MMU_IN[13]\: IBUF port map (
+ O => MMU_IN_C_C(13),
+ I0 => MMU_IN(13));
+ \II_MMU_IN[14]\: IBUF port map (
+ O => MMU_IN_C_C(14),
+ I0 => MMU_IN(14));
+ \II_MMU_IN[15]\: IBUF port map (
+ O => MMU_IN_C_C(15),
+ I0 => MMU_IN(15));
+ \II_MMU_OUT[12]\: OBUF port map (
+ O => MMU_OUT(12),
+ I0 => MMU_IN_C_C(12));
+ \II_MMU_OUT[13]\: OBUF port map (
+ O => MMU_OUT(13),
+ I0 => MMU_IN_C_C(13));
+ \II_MMU_OUT[14]\: OBUF port map (
+ O => MMU_OUT(14),
+ I0 => MMU_IN_C_C(14));
+ \II_MMU_OUT[15]\: OBUF port map (
+ O => MMU_OUT(15),
+ I0 => MMU_IN_C_C(15));
+ II_IORQ: IBUF port map (
+ O => IORQ_C,
+ I0 => IORQ);
+ II_CSROML: OBUF port map (
+ O => CSROML,
+ I0 => OP_GE_UN24_CSROMH_I_C);
+ II_CSROMH: OBUF port map (
+ O => CSROMH,
+ I0 => UN12_CSROMH_I_C);
+ II_CSRAM: OBUF port map (
+ O => CSRAM,
+ I0 => MMU_IN_I_C(15));
+ II_CSUART: OBUF port map (
+ O => CSUART,
+ I0 => GND);
+ II_CSCTC: OBUF port map (
+ O => CSCTC,
+ I0 => GND);
+ II_CSPIO: OBUF port map (
+ O => CSPIO,
+ I0 => N_181_I_0_C);
+ II_UN26_CSPIO: AND2 port map (
+ O => N_181,
+ I0 => OP_LT_UN11_CSPIO,
+ I1 => N_184);
+ \II_UN26_CSPIO.G_184\: AND2 port map (
+ O => N_184,
+ I0 => MMU_IN_C(4),
+ I1 => IORQ_I);
+ \II_MMU_IN_I[6]\: INV port map (
+ O => MMU_IN_I_0(6),
+ I0 => MMU_IN_C(6));
+ \II_MMU_IN_I[5]\: INV port map (
+ O => MMU_IN_I_0(5),
+ I0 => MMU_IN_C(5));
+ \II_MMU_IN_I[3]\: INV port map (
+ O => MMU_IN_I_0(3),
+ I0 => MMU_IN_C(3));
+ \II_MMU_IN_I[2]\: INV port map (
+ O => MMU_IN_I_0(2),
+ I0 => MMU_IN_C(2));
+ \II_MMU_IN_I[14]\: INV port map (
+ O => MMU_IN_I_0(14),
+ I0 => MMU_IN_C_C(14));
+ \II_MMU_IN_I[13]\: INV port map (
+ O => MMU_IN_I_0(13),
+ I0 => MMU_IN_C_C(13));
+ II_UN12_CSROMH: AND2 port map (
+ O => UN12_CSROMH,
+ I0 => OP_LT_UN11_CSROMH,
+ I1 => OP_GE_UN24_CSROMH_I_C);
+ II_G_116: AND2 port map (
+ O => N_117,
+ I0 => MMU_IN_I_0(14),
+ I1 => MMU_IN_I_0(13));
+ II_G_118: AND2 port map (
+ O => OP_GE_UN24_CSROMH,
+ I0 => MMU_IN_I_C(15),
+ I1 => N_117);
+ II_G_179: AND2 port map (
+ O => OP_LT_UN11_CSROMH,
+ I0 => MMU_IN_I_C(15),
+ I1 => MMU_IN_I_0(14));
+ II_G_49: AND2 port map (
+ O => N_51,
+ I0 => MMU_IN_I_0(3),
+ I1 => MMU_IN_I_0(2));
+ II_G_53: AND2 port map (
+ O => N_54,
+ I0 => N_51,
+ I1 => MMU_IN_I_0(5));
+ II_G_55: AND2 port map (
+ O => N_56,
+ I0 => N_54,
+ I1 => MMU_IN_I_0(6));
+ II_G_57: AND2 port map (
+ O => OP_LT_UN11_CSPIO,
+ I0 => N_56,
+ I1 => MMU_IN_I_0(7));
+ II_N_181_I: INV port map (
+ O => N_181_I_0_C,
+ I0 => N_181);
+ \II_MMU_IN_I[15]\: INV port map (
+ O => MMU_IN_I_C(15),
+ I0 => MMU_IN_C_C(15));
+ II_UN12_CSROMH_I: INV port map (
+ O => UN12_CSROMH_I_C,
+ I0 => UN12_CSROMH);
+ II_OP_GE_UN24_CSROMH_I: INV port map (
+ O => OP_GE_UN24_CSROMH_I_C,
+ I0 => OP_GE_UN24_CSROMH);
+ II_IORQ_I: INV port map (
+ O => IORQ_I,
+ I0 => IORQ_C);
+ \II_MMU_IN_I[7]\: INV port map (
+ O => MMU_IN_I_0(7),
+ I0 => MMU_IN_C(7));
+ VCC <= '1';
+end beh;
+
diff --git a/sw/cpld/address_decoder.vho b/sw/cpld/address_decoder.vho new file mode 100755 index 0000000..ef46479 --- /dev/null +++ b/sw/cpld/address_decoder.vho @@ -0,0 +1,131 @@ +-- VHDL netlist-file
+library mach;
+use mach.components.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity address_decoder is
+ port (
+ CSROML : out std_logic;
+ CSROMH : out std_logic;
+ CSRAM : out std_logic;
+ CSUART : out std_logic;
+ CSCTC : out std_logic;
+ CSPIO : out std_logic;
+ MMU_IN : in std_logic_vector(15 downto 0);
+ MMU_OUT : out std_logic_vector(15 downto 12)
+ );
+end address_decoder;
+
+architecture NetList of address_decoder is
+
+ signal MMU_IN_15_PIN : std_logic;
+ signal MMU_OUT_15_COM : std_logic;
+ signal CSROML_COM : std_logic;
+ signal CSROMH_COM : std_logic;
+ signal CSRAM_COM : std_logic;
+ signal CSUART_COM : std_logic;
+ signal CSCTC_COM : std_logic;
+ signal CSPIO_COM : std_logic;
+ signal MMU_IN_14_PIN : std_logic;
+ signal MMU_IN_13_PIN : std_logic;
+ signal MMU_IN_12_PIN : std_logic;
+ signal MMU_IN_11_PIN : std_logic;
+ signal MMU_IN_10_PIN : std_logic;
+ signal MMU_IN_9_PIN : std_logic;
+ signal MMU_IN_8_PIN : std_logic;
+ signal MMU_IN_7_PIN : std_logic;
+ signal MMU_IN_6_PIN : std_logic;
+ signal MMU_IN_5_PIN : std_logic;
+ signal MMU_IN_4_PIN : std_logic;
+ signal MMU_IN_3_PIN : std_logic;
+ signal MMU_IN_2_PIN : std_logic;
+ signal MMU_OUT_14_COM : std_logic;
+ signal MMU_OUT_13_COM : std_logic;
+ signal MMU_OUT_12_COM : std_logic;
+ signal T_0 : std_logic;
+ signal T_1 : std_logic;
+ signal T_2 : std_logic;
+ signal T_3 : std_logic;
+ signal T_4 : std_logic;
+ signal T_5 : std_logic;
+ signal T_6 : std_logic;
+ signal T_7 : std_logic;
+ signal T_8 : std_logic;
+ signal T_9 : std_logic;
+ signal T_10 : std_logic;
+ signal T_11 : std_logic;
+ signal T_12 : std_logic;
+ signal T_13 : std_logic;
+ signal T_14 : std_logic;
+ signal T_15 : std_logic;
+ signal T_16 : std_logic;
+ signal GATE_T_1_A : std_logic;
+ signal GATE_T_1_B : std_logic;
+ signal GATE_T_5_A : std_logic;
+ signal GATE_T_8_A : std_logic;
+ signal GATE_T_9_A : std_logic;
+ signal GATE_T_12_A : std_logic;
+ signal GATE_T_14_DN : std_logic;
+
+begin
+ IN_MMU_IN_15_I_1: IBUF port map ( O=>MMU_IN_15_PIN, I0=>MMU_IN(15) );
+ OUT_MMU_OUT_15_I_1: OBUF port map ( O=>MMU_OUT(15), I0=>MMU_OUT_15_COM );
+ OUT_CSROML_I_1: OBUF port map ( O=>CSROML, I0=>CSROML_COM );
+ OUT_CSROMH_I_1: OBUF port map ( O=>CSROMH, I0=>CSROMH_COM );
+ OUT_CSRAM_I_1: OBUF port map ( O=>CSRAM, I0=>CSRAM_COM );
+ OUT_CSUART_I_1: OBUF port map ( O=>CSUART, I0=>CSUART_COM );
+ OUT_CSCTC_I_1: OBUF port map ( O=>CSCTC, I0=>CSCTC_COM );
+ OUT_CSPIO_I_1: OBUF port map ( O=>CSPIO, I0=>CSPIO_COM );
+ IN_MMU_IN_14_I_1: IBUF port map ( O=>MMU_IN_14_PIN, I0=>MMU_IN(14) );
+ IN_MMU_IN_13_I_1: IBUF port map ( O=>MMU_IN_13_PIN, I0=>MMU_IN(13) );
+ IN_MMU_IN_12_I_1: IBUF port map ( O=>MMU_IN_12_PIN, I0=>MMU_IN(12) );
+ IN_MMU_IN_11_I_1: IBUF port map ( O=>MMU_IN_11_PIN, I0=>MMU_IN(11) );
+ IN_MMU_IN_10_I_1: IBUF port map ( O=>MMU_IN_10_PIN, I0=>MMU_IN(10) );
+ IN_MMU_IN_9_I_1: IBUF port map ( O=>MMU_IN_9_PIN, I0=>MMU_IN(9) );
+ IN_MMU_IN_8_I_1: IBUF port map ( O=>MMU_IN_8_PIN, I0=>MMU_IN(8) );
+ IN_MMU_IN_7_I_1: IBUF port map ( O=>MMU_IN_7_PIN, I0=>MMU_IN(7) );
+ IN_MMU_IN_6_I_1: IBUF port map ( O=>MMU_IN_6_PIN, I0=>MMU_IN(6) );
+ IN_MMU_IN_5_I_1: IBUF port map ( O=>MMU_IN_5_PIN, I0=>MMU_IN(5) );
+ IN_MMU_IN_4_I_1: IBUF port map ( O=>MMU_IN_4_PIN, I0=>MMU_IN(4) );
+ IN_MMU_IN_3_I_1: IBUF port map ( O=>MMU_IN_3_PIN, I0=>MMU_IN(3) );
+ IN_MMU_IN_2_I_1: IBUF port map ( O=>MMU_IN_2_PIN, I0=>MMU_IN(2) );
+ OUT_MMU_OUT_14_I_1: OBUF port map ( O=>MMU_OUT(14), I0=>MMU_OUT_14_COM );
+ OUT_MMU_OUT_13_I_1: OBUF port map ( O=>MMU_OUT(13), I0=>MMU_OUT_13_COM );
+ OUT_MMU_OUT_12_I_1: OBUF port map ( O=>MMU_OUT(12), I0=>MMU_OUT_12_COM );
+ GATE_MMU_OUT_15_I_1: BUFF port map ( I0=>MMU_IN_15_PIN, O=>MMU_OUT_15_COM );
+ GATE_T_0_I_1: NOR3 port map ( O=>T_0, I2=>MMU_IN_14_PIN, I1=>MMU_IN_15_PIN, I0=>MMU_IN_13_PIN );
+ GATE_T_1_I_1: INV port map ( I0=>MMU_IN_14_PIN, O=>GATE_T_1_A );
+ GATE_T_1_I_2: INV port map ( I0=>MMU_IN_15_PIN, O=>GATE_T_1_B );
+ GATE_T_1_I_3: AND3 port map ( O=>T_1, I0=>MMU_IN_13_PIN, I2=>GATE_T_1_A, I1=>GATE_T_1_B );
+ GATE_CSRAM_I_1: INV port map ( I0=>MMU_IN_15_PIN, O=>CSRAM_COM );
+ GATE_T_2_I_1: AND4 port map ( O=>T_2, I3=>T_13, I2=>T_14, I1=>T_15, I0=>T_16 );
+ GATE_T_3_I_1: AND4 port map ( O=>T_3, I3=>T_9, I2=>T_10, I1=>T_11, I0=>T_12 );
+ GATE_T_4_I_1: AND4 port map ( O=>T_4, I3=>T_5, I2=>T_6, I1=>T_7, I0=>T_8 );
+ GATE_MMU_OUT_14_I_1: BUFF port map ( I0=>MMU_IN_14_PIN, O=>MMU_OUT_14_COM );
+ GATE_MMU_OUT_13_I_1: BUFF port map ( I0=>MMU_IN_13_PIN, O=>MMU_OUT_13_COM );
+ GATE_MMU_OUT_12_I_1: BUFF port map ( I0=>MMU_IN_12_PIN, O=>MMU_OUT_12_COM );
+ GATE_CSROML_I_1: INV port map ( I0=>T_0, O=>CSROML_COM );
+ GATE_CSROMH_I_1: INV port map ( I0=>T_1, O=>CSROMH_COM );
+ GATE_CSUART_I_1: INV port map ( I0=>T_2, O=>CSUART_COM );
+ GATE_CSCTC_I_1: INV port map ( I0=>T_3, O=>CSCTC_COM );
+ GATE_CSPIO_I_1: INV port map ( I0=>T_4, O=>CSPIO_COM );
+ GATE_T_5_I_1: AND2 port map ( O=>T_5, I1=>MMU_IN_9_PIN, I0=>GATE_T_5_A );
+ GATE_T_5_I_2: INV port map ( O=>GATE_T_5_A, I0=>MMU_IN_8_PIN );
+ GATE_T_6_I_1: NOR2 port map ( O=>T_6, I1=>MMU_IN_10_PIN, I0=>MMU_IN_11_PIN );
+ GATE_T_7_I_1: NOR2 port map ( O=>T_7, I1=>MMU_IN_12_PIN, I0=>MMU_IN_13_PIN );
+ GATE_T_8_I_1: AND2 port map ( O=>T_8, I1=>MMU_IN_14_PIN, I0=>GATE_T_8_A );
+ GATE_T_8_I_2: INV port map ( O=>GATE_T_8_A, I0=>MMU_IN_15_PIN );
+ GATE_T_9_I_1: AND2 port map ( O=>T_9, I1=>MMU_IN_8_PIN, I0=>GATE_T_9_A );
+ GATE_T_9_I_2: INV port map ( O=>GATE_T_9_A, I0=>MMU_IN_9_PIN );
+ GATE_T_10_I_1: NOR2 port map ( O=>T_10, I1=>MMU_IN_10_PIN, I0=>MMU_IN_11_PIN );
+ GATE_T_11_I_1: NOR2 port map ( O=>T_11, I1=>MMU_IN_12_PIN, I0=>MMU_IN_13_PIN );
+ GATE_T_12_I_1: AND2 port map ( O=>T_12, I1=>MMU_IN_14_PIN, I0=>GATE_T_12_A );
+ GATE_T_12_I_2: INV port map ( O=>GATE_T_12_A, I0=>MMU_IN_15_PIN );
+ GATE_T_13_I_1: NOR2 port map ( O=>T_13, I1=>MMU_IN_2_PIN, I0=>MMU_IN_3_PIN );
+ GATE_T_14_I_1: NOR4 port map ( I0=>MMU_IN_7_PIN, I1=>MMU_IN_6_PIN, O=>T_14, I2=>MMU_IN_5_PIN, I3=>GATE_T_14_DN );
+ GATE_T_14_I_2: INV port map ( I0=>MMU_IN_4_PIN, O=>GATE_T_14_DN );
+ GATE_T_15_I_14: NOR4 port map ( O=>T_15, I3=>MMU_IN_8_PIN, I2=>MMU_IN_9_PIN, I1=>MMU_IN_10_PIN, I0=>MMU_IN_11_PIN );
+ GATE_T_16_I_14: NOR4 port map ( O=>T_16, I3=>MMU_IN_12_PIN, I2=>MMU_IN_13_PIN, I1=>MMU_IN_14_PIN, I0=>MMU_IN_15_PIN );
+
+end NetList;
diff --git a/sw/cpld/address_decoder.vm b/sw/cpld/address_decoder.vm new file mode 100755 index 0000000..d4ee62b --- /dev/null +++ b/sw/cpld/address_decoder.vm @@ -0,0 +1,317 @@ +//
+// Written by Synplify
+// Thu Nov 23 11:54:35 2017
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "noname"
+// file 1 "\c:\isptools\synpbase\lib\vhd\std.vhd "
+// file 2 "\c:\_prossn\cpld.nao\address_decoder.vhd "
+// file 3 "\c:\isptools\synpbase\lib\vhd\std1164.vhd "
+// file 4 "\c:\isptools\synpbase\lib\vhd\arith.vhd "
+// file 5 "\c:\isptools\synpbase\lib\vhd\unsigned.vhd "
+
+`timescale 100 ps/100 ps
+module IBUF (
+ O,
+ I0
+);
+output O;
+input I0;
+wire O ;
+wire I0 ;
+wire true ;
+wire false ;
+ assign #(1) O = I0;
+ assign true = 1'b1;
+ assign false = 1'b0;
+endmodule /* IBUF */
+
+module OBUF (
+ O,
+ I0
+);
+output O;
+input I0;
+wire O ;
+wire I0 ;
+wire true ;
+wire false ;
+ assign #(1) O = I0;
+ assign true = 1'b1;
+ assign false = 1'b0;
+endmodule /* OBUF */
+
+module AND2 (
+ O,
+ I0,
+ I1
+);
+output O;
+input I0;
+input I1;
+wire O ;
+wire I0 ;
+wire I1 ;
+wire true ;
+wire false ;
+ assign true = 1'b1;
+ assign false = 1'b0;
+ assign #(1) O = I0 & I1 ;
+endmodule /* AND2 */
+
+module INV (
+ O,
+ I0
+);
+output O;
+input I0;
+wire O ;
+wire I0 ;
+wire true ;
+wire false ;
+ assign #(1) O = ~ I0;
+ assign true = 1'b1;
+ assign false = 1'b0;
+endmodule /* INV */
+
+module ADDRESS_DECODER (
+ MMU_IN,
+ MMU_OUT,
+ IORQ,
+ RD,
+ CSROML,
+ CSROMH,
+ CSRAM,
+ CSUART,
+ CSCTC,
+ CSPIO
+);
+input [15:0] MMU_IN;
+output [15:12] MMU_OUT;
+input IORQ;
+input RD;
+output CSROML;
+output CSROMH;
+output CSRAM;
+output CSUART;
+output CSCTC;
+output CSPIO;
+wire [15:0] MMU_IN;
+wire [15:12] MMU_OUT;
+wire IORQ ;
+wire RD ;
+wire CSROML ;
+wire CSROMH ;
+wire CSRAM ;
+wire CSUART ;
+wire CSCTC ;
+wire CSPIO ;
+wire [14:2] MMU_IN_i_0;
+wire [7:2] MMU_IN_c;
+wire [15:12] MMU_IN_c_c;
+wire [15:15] MMU_IN_i_c;
+wire op_ge_un24_csromh ;
+wire op_lt_un11_csromh ;
+wire un12_csromh ;
+wire N_117 ;
+wire N_181 ;
+wire op_lt_un11_cspio ;
+wire N_56 ;
+wire N_54 ;
+wire N_51 ;
+wire IORQ_i ;
+wire IORQ_c ;
+wire op_ge_un24_csromh_i_c ;
+wire un12_csromh_i_c ;
+wire N_181_i_0_c ;
+wire GND ;
+wire N_184 ;
+wire VCC ;
+//@1:1
+ assign GND = 1'b0;
+ IBUF \MMU_IN_Z[2] (
+ .O(MMU_IN_c[2]),
+ .I0(MMU_IN[2])
+);
+ IBUF \MMU_IN_Z[3] (
+ .O(MMU_IN_c[3]),
+ .I0(MMU_IN[3])
+);
+ IBUF \MMU_IN_Z[4] (
+ .O(MMU_IN_c[4]),
+ .I0(MMU_IN[4])
+);
+ IBUF \MMU_IN_Z[5] (
+ .O(MMU_IN_c[5]),
+ .I0(MMU_IN[5])
+);
+ IBUF \MMU_IN_Z[6] (
+ .O(MMU_IN_c[6]),
+ .I0(MMU_IN[6])
+);
+ IBUF \MMU_IN_Z[7] (
+ .O(MMU_IN_c[7]),
+ .I0(MMU_IN[7])
+);
+ IBUF \MMU_IN_Z[12] (
+ .O(MMU_IN_c_c[12]),
+ .I0(MMU_IN[12])
+);
+ IBUF \MMU_IN_Z[13] (
+ .O(MMU_IN_c_c[13]),
+ .I0(MMU_IN[13])
+);
+ IBUF \MMU_IN_Z[14] (
+ .O(MMU_IN_c_c[14]),
+ .I0(MMU_IN[14])
+);
+ IBUF \MMU_IN_Z[15] (
+ .O(MMU_IN_c_c[15]),
+ .I0(MMU_IN[15])
+);
+ OBUF \MMU_OUT_Z[12] (
+ .O(MMU_OUT[12]),
+ .I0(MMU_IN_c_c[12])
+);
+ OBUF \MMU_OUT_Z[13] (
+ .O(MMU_OUT[13]),
+ .I0(MMU_IN_c_c[13])
+);
+ OBUF \MMU_OUT_Z[14] (
+ .O(MMU_OUT[14]),
+ .I0(MMU_IN_c_c[14])
+);
+ OBUF \MMU_OUT_Z[15] (
+ .O(MMU_OUT[15]),
+ .I0(MMU_IN_c_c[15])
+);
+ IBUF IORQ_Z (
+ .O(IORQ_c),
+ .I0(IORQ)
+);
+ OBUF CSROML_Z (
+ .O(CSROML),
+ .I0(op_ge_un24_csromh_i_c)
+);
+ OBUF CSROMH_Z (
+ .O(CSROMH),
+ .I0(un12_csromh_i_c)
+);
+ OBUF CSRAM_Z (
+ .O(CSRAM),
+ .I0(MMU_IN_i_c[15])
+);
+ OBUF CSUART_Z (
+ .O(CSUART),
+ .I0(GND)
+);
+ OBUF CSCTC_Z (
+ .O(CSCTC),
+ .I0(GND)
+);
+ OBUF CSPIO_Z (
+ .O(CSPIO),
+ .I0(N_181_i_0_c)
+);
+ AND2 un26_cspio (
+ .O(N_181),
+ .I0(op_lt_un11_cspio),
+ .I1(N_184)
+);
+ AND2 \un26_cspio.G_184 (
+ .O(N_184),
+ .I0(MMU_IN_c[4]),
+ .I1(IORQ_i)
+);
+ INV \MMU_IN_i[6] (
+ .O(MMU_IN_i_0[6]),
+ .I0(MMU_IN_c[6])
+);
+ INV \MMU_IN_i[5] (
+ .O(MMU_IN_i_0[5]),
+ .I0(MMU_IN_c[5])
+);
+ INV \MMU_IN_i[3] (
+ .O(MMU_IN_i_0[3]),
+ .I0(MMU_IN_c[3])
+);
+ INV \MMU_IN_i[2] (
+ .O(MMU_IN_i_0[2]),
+ .I0(MMU_IN_c[2])
+);
+ INV \MMU_IN_i[14] (
+ .O(MMU_IN_i_0[14]),
+ .I0(MMU_IN_c_c[14])
+);
+ INV \MMU_IN_i[13] (
+ .O(MMU_IN_i_0[13]),
+ .I0(MMU_IN_c_c[13])
+);
+ AND2 un12_csromh_Z (
+ .O(un12_csromh),
+ .I0(op_lt_un11_csromh),
+ .I1(op_ge_un24_csromh_i_c)
+);
+ AND2 G_116 (
+ .O(N_117),
+ .I0(MMU_IN_i_0[14]),
+ .I1(MMU_IN_i_0[13])
+);
+ AND2 G_118 (
+ .O(op_ge_un24_csromh),
+ .I0(MMU_IN_i_c[15]),
+ .I1(N_117)
+);
+ AND2 G_179 (
+ .O(op_lt_un11_csromh),
+ .I0(MMU_IN_i_c[15]),
+ .I1(MMU_IN_i_0[14])
+);
+ AND2 G_49 (
+ .O(N_51),
+ .I0(MMU_IN_i_0[3]),
+ .I1(MMU_IN_i_0[2])
+);
+ AND2 G_53 (
+ .O(N_54),
+ .I0(N_51),
+ .I1(MMU_IN_i_0[5])
+);
+ AND2 G_55 (
+ .O(N_56),
+ .I0(N_54),
+ .I1(MMU_IN_i_0[6])
+);
+ AND2 G_57 (
+ .O(op_lt_un11_cspio),
+ .I0(N_56),
+ .I1(MMU_IN_i_0[7])
+);
+ INV N_181_i (
+ .O(N_181_i_0_c),
+ .I0(N_181)
+);
+ INV \MMU_IN_i[15] (
+ .O(MMU_IN_i_c[15]),
+ .I0(MMU_IN_c_c[15])
+);
+ INV un12_csromh_i (
+ .O(un12_csromh_i_c),
+ .I0(un12_csromh)
+);
+ INV op_ge_un24_csromh_i (
+ .O(op_ge_un24_csromh_i_c),
+ .I0(op_ge_un24_csromh)
+);
+ INV IORQ_i_Z (
+ .O(IORQ_i),
+ .I0(IORQ_c)
+);
+ INV \MMU_IN_i[7] (
+ .O(MMU_IN_i_0[7]),
+ .I0(MMU_IN_c[7])
+);
+ assign VCC = 1'b1;
+endmodule /* ADDRESS_DECODER */
+
diff --git a/sw/cpld/address_decoder.xrf b/sw/cpld/address_decoder.xrf new file mode 100755 index 0000000..1b22f54 --- /dev/null +++ b/sw/cpld/address_decoder.xrf @@ -0,0 +1,16 @@ +Signal Name Cross Reference File
+
+ispDesignEXPERT 8.3.02.12
+
+Design 'address_decoder' created Thu Nov 23 11:54:43 2017
+
+
+ LEGEND: '>' Functional Block Port Separator
+ '/' Hierarchy Path Separator
+ '@' Automatically Generated Node
+
+
+Short Name Hierarchical Name
+---------- -----------------
+
+ *** Shortened names not required for this design. ***
diff --git a/sw/cpld/address_decoder_chain.xcf b/sw/cpld/address_decoder_chain.xcf new file mode 100755 index 0000000..519e8a3 --- /dev/null +++ b/sw/cpld/address_decoder_chain.xcf @@ -0,0 +1,53 @@ +<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="13.2">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Vendor>Vantis</Vendor>
+ <Family>MACH4</Family>
+ <Name>M4-32/32</Name>
+ <IDCode>0x07430157</IDCode>
+ <Package>44-pin PLCC</Package>
+ <PON>M4-32/32-XXJC</PON>
+ <Bypass>
+ <InstrLen>6</InstrLen>
+ <InstrVal>010001</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>C:\_prossn\cpld\address_decoder.jed</File>
+ <FileTime>10/20/17 10:38:09</FileTime>
+ <JedecChecksum>0xC3E6</JedecChecksum>
+ <Operation>Erase,Program,Verify</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>98</PreloadLength>
+ <IOVectorData>0x0000000000000000000000000</IOVectorData>
+ <Reinitialize value="TRUE"/>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
diff --git a/sw/cpld/automake.log b/sw/cpld/automake.log index 700da07..3f20cc0 100644..100755 --- a/sw/cpld/automake.log +++ b/sw/cpld/automake.log @@ -1,6 +1,7 @@ -ispLEVER Auto-Make Log File ---------------------------- - -Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\checkini.exe -err=automake.err "C:\ispLEVER_Classic2\ispcpld\config\lc.ini"' - -Done: completed successfully. +ispDesignEXPERT Auto-Make Log File
+----------------------------------
+
+Updating: Post-Fit Pinouts
+
+Launching: 'C:\ispTOOLS\ispsys\bin\devedit.exe @address_decoder.rs3'
+
diff --git a/sw/cpld_test/.tmp_log b/sw/cpld/stderr.log index e69de29..e69de29 100644..100755 --- a/sw/cpld_test/.tmp_log +++ b/sw/cpld/stderr.log diff --git a/sw/cpld_test/cpld_test.naf b/sw/cpld/stdout.log index e69de29..e69de29 100644..100755 --- a/sw/cpld_test/cpld_test.naf +++ b/sw/cpld/stdout.log diff --git a/sw/cpld/syndos.env b/sw/cpld/syndos.env new file mode 100755 index 0000000..2977a55 --- /dev/null +++ b/sw/cpld/syndos.env @@ -0,0 +1,24 @@ +DIOEDA_AppNotes=C:\ISPTOOLS\ISPSYS\APPNOTES
+DIOEDA_Bin=C:\ISPTOOLS\ISPSYS\BIN
+DIOEDA_Config=C:\ISPTOOLS\ISPSYS\CONFIG
+DIOEDA_Examples=C:\ISPTOOLS\ISPSYS\EXAMPLES
+DIOEDA_License=C:\ISPTOOLS\ISPCOMP\LICENSE
+DIOEDA_MachPath=C:\ISPTOOLS\ISPSYS\BIN
+DIOEDA_Manuals=C:\ISPTOOLS\ISPSYS\MANUALS
+DIOEDA_ModelsimPath=C:\ISPTOOLS\MODELSIM\WIN32LOEM
+DIOEDA_PDSPath=C:\ISPTOOLS\ISPCOMP
+DIOEDA_Root=C:\ISPTOOLS\ISPSYS
+DIOEDA_SpectrumPath=C:\ISPTOOLS\SPECTRUM
+DIOEDA_SynplifyPath=C:\ISPTOOLS\SYNPBASE
+DIOEDA_Tutorial=C:\ISPTOOLS\ISPSYS\TUTORIAL
+DIOEDA_ABEL5DEV=C:\ISPTOOLS\ISPSYS\LIB5
+DIOEDA_ProductName=ispDesignEXPERT
+DIOEDA_ProductPrefix=SYN
+DIOEDA_ProductTitle=ispDesignEXPERT
+DIOEDA_ProductType=HDL-BASE
+DIOEDA_ProductVersion=8.3.02.12_DE_HDL_BASE
+DIOEDA_TimingSim=LatticeLogicSim
+DIOEDA_CONTEXT=8.3
+DIOPRODUCT=ispDesignEXPERT
+ABEL5DEV=C:\ISPTOOLS\ISPSYS\LIB5
+PATH=C:\ISPTOOLS\ISPSYS\BIN
diff --git a/sw/cpld_test/automake.log b/sw/cpld_test/automake.log deleted file mode 100644 index f33bc75..0000000 --- a/sw/cpld_test/automake.log +++ /dev/null @@ -1,41 +0,0 @@ -ispLEVER Auto-Make Log File ---------------------------- - -Updating: Pre-Fit Equations - -Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\Synpwrap.exe -e cpld_test -target mach -pro ' - -Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. -Version : 2.0.00.17.20.15 - -Done sucessfully with exit code 2. -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] - -Error output EDIF file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi -Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 - -Done: failed with exit code: 0002. diff --git a/sw/cpld_test/cpld_test.STY b/sw/cpld_test/cpld_test.STY deleted file mode 100644 index 3b3c6ba..0000000 --- a/sw/cpld_test/cpld_test.STY +++ /dev/null @@ -1,22 +0,0 @@ -[Normal] -synlibXRef=lc4k_pvhd, VHDL.TASKLSVhd, 0, Yes -_EdfFrequency=lc4k_pvhd, VHDL.TASKLSVhd, 0, 200 -_EdfInConsFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, -_EdfSymFSM=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfFanin=lc4k_pvhd, VHDL.TASKLSVhd, 0, 20 -_EdfMaxMacrocell=lc4k_pvhd, VHDL.TASKLSVhd, 0, 16 -_EdfPerDesignOptTiming=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 -_EdfOutputPreFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfMapLogic=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -_EdfInsertIO=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -_EdfOutNetForm=lc4k_pvhd, VHDL.TASKLSVhd, 0, None -_EdfNumCritPath=lc4k_pvhd, VHDL.TASKLSVhd, 0, 3 -_EdfUnconsClk=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfNumStartEnd=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 -_EdfResSharing=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfPushTirstates=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfDefEnumEncode=lc4k_pvhd, VHDL.TASKLSVhd, 0, default -_EdfArrangeVHDLFiles=lc4k_pvhd, VHDL.TASKLSVhd, 0, True -_EdfSynOnOffImp=lc4k_pvhd, VHDL.TASKLSVhd, 0, False -[STRATEGY-LIST] -Normal=True, 1496317751 diff --git a/sw/cpld_test/cpld_test.htm b/sw/cpld_test/cpld_test.htm deleted file mode 100644 index 365f96f..0000000 --- a/sw/cpld_test/cpld_test.htm +++ /dev/null @@ -1,9 +0,0 @@ -<html> - <head> - <title>syntmp/cpld_test_srr.htm log file</title> - </head> - <frameset cols="20%, 80%"> - <frame src="syntmp/cpld_test_toc.htm" name="tocFrame" /> - <frame src="syntmp/cpld_test_srr.htm" name="srrFrame"/> -</frameset> - </html> diff --git a/sw/cpld_test/cpld_test.jhd b/sw/cpld_test/cpld_test.jhd deleted file mode 100644 index 9be00a5..0000000 --- a/sw/cpld_test/cpld_test.jhd +++ /dev/null @@ -1,3 +0,0 @@ - - -MODULE cpld_test diff --git a/sw/cpld_test/cpld_test.jid b/sw/cpld_test/cpld_test.jid deleted file mode 100644 index c77ab04..0000000 --- a/sw/cpld_test/cpld_test.jid +++ /dev/null @@ -1 +0,0 @@ -. cpld_test cpld_test.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd diff --git a/sw/cpld_test/cpld_test.lci b/sw/cpld_test/cpld_test.lci deleted file mode 100644 index 62d7d9d..0000000 --- a/sw/cpld_test/cpld_test.lci +++ /dev/null @@ -1,63 +0,0 @@ -[Device] -Family=M4A5; -PartNumber=M4A5-32/32-10JC; -Package=44PLCC; -PartType=M4A5-32/32; -Speed=-10; -Operating_condition=COM; -Status=Production; - -[Revision] -Parent=m4a5.lci; -DATE=06/01/2017; -TIME=13:49:11; -Source_Format=Pure_VHDL; -Synthesis=Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -Layer = Off; - -[Group Assignments] -Layer = Off; - -[Resource Reservations] -Layer = Off; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] - -[IO Types] -Layer = off; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - - diff --git a/sw/cpld_test/cpld_test.lct b/sw/cpld_test/cpld_test.lct deleted file mode 100644 index 62d7d9d..0000000 --- a/sw/cpld_test/cpld_test.lct +++ /dev/null @@ -1,63 +0,0 @@ -[Device] -Family=M4A5; -PartNumber=M4A5-32/32-10JC; -Package=44PLCC; -PartType=M4A5-32/32; -Speed=-10; -Operating_condition=COM; -Status=Production; - -[Revision] -Parent=m4a5.lci; -DATE=06/01/2017; -TIME=13:49:11; -Source_Format=Pure_VHDL; -Synthesis=Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -Layer = Off; - -[Group Assignments] -Layer = Off; - -[Resource Reservations] -Layer = Off; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] - -[IO Types] -Layer = off; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - - diff --git a/sw/cpld_test/cpld_test.lct.bak b/sw/cpld_test/cpld_test.lct.bak deleted file mode 100644 index 4bdf950..0000000 --- a/sw/cpld_test/cpld_test.lct.bak +++ /dev/null @@ -1,113 +0,0 @@ - -[Device] -Family = lc4k; -PartNumber = LC4064ZE-5UMN64C; -Package = 64ucBGA; -PartType = LC4064ZE; -Speed = -5.8; -Operating_condition = COM; -Status = Production; - -[Revision] -Parent = lc4k64e.lci; -DATE = 2002; -TIME = 0:00:00; -Source_Format = Pure_VHDL; -Synthesis = Synplify; - -[Ignore Assignments] - -[Clear Assignments] - -[Backannotate Assignments] - -[Global Constraints] - -[Location Assignments] -layer = OFF; - -[Group Assignments] -layer = OFF; - -[Resource Reservations] -layer = OFF; - -[Fitter Report Format] - -[Power] - -[Source Constraint Option] - -[Fast Bypass] - -[OSM Bypass] - -[Input Registers] - -[Netlist/Delay Format] -NetList = VHDL; - -[IO Types] -layer = OFF; - -[Pullup] - -[Slewrate] - -[Region] - -[Timing Constraints] - -[HSI Attributes] - -[Input Delay] - -[opt global constraints list] - -[Explorer User Settings] - -[Pin attributes list] - -[global constraints list] - -[Global Constraints Process Update] - -[pin lock limitation] - -[LOCATION ASSIGNMENTS LIST] - -[RESOURCE RESERVATIONS LIST] - -[individual constraints list] - -[Attributes list setting] - -[Timing Analyzer] - -[PLL Assignments] - -[Dual Function Macrocell] - -[Explorer Results] - -[VHDL synplify constraints] - -[VHDL spectrum constraints] - -[verilog synplify constraints] - -[verilog spectrum constraints] - -[VHDL synplify constraints list] - -[VHDL spectrum constraints list] - -[verilog synplify constraints list] - -[verilog spectrum constraints list] - -[Power Guard] - -[ORP Bypass] - -[Register Powerup] diff --git a/sw/cpld_test/cpld_test.prj b/sw/cpld_test/cpld_test.prj deleted file mode 100644 index eb5548a..0000000 --- a/sw/cpld_test/cpld_test.prj +++ /dev/null @@ -1,34 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj -#-- Written on Thu Jun 01 13:51:28 2017 - - -#device options -set_option -technology mach -set_option -part M4A5-32 - -#compilation/mapping options - -#map options - -#simulation options -set_option -write_verilog false -set_option -write_vhdl false - -#timing analysis options -set_option -synthesis_onoff_pragma false - -#-- add_file options -add_file -vhdl -lib work "cpld_test.vhd" - -#-- top module name -set_option -top_module cpld_test - -#-- set result format/file last -project -result_file "cpld_test.edi" - -#-- error message log file -project -log_file cpld_test.srf - -#-- run Synplify with 'arrange VHDL file' -project -run diff --git a/sw/cpld_test/cpld_test.rev b/sw/cpld_test/cpld_test.rev deleted file mode 100644 index e8bfb3d..0000000 --- a/sw/cpld_test/cpld_test.rev +++ /dev/null @@ -1,3 +0,0 @@ -<SYNPROJ_Revision_Control> -<RevisionControl_Info/> -</SYNPROJ_Revision_Control> diff --git a/sw/cpld_test/cpld_test.srf b/sw/cpld_test/cpld_test.srf deleted file mode 100644 index 801fff8..0000000 --- a/sw/cpld_test/cpld_test.srf +++ /dev/null @@ -1,25 +0,0 @@ -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] diff --git a/sw/cpld_test/cpld_test.srr b/sw/cpld_test/cpld_test.srr deleted file mode 100644 index 801fff8..0000000 --- a/sw/cpld_test/cpld_test.srr +++ /dev/null @@ -1,25 +0,0 @@ -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] diff --git a/sw/cpld_test/cpld_test.syn b/sw/cpld_test/cpld_test.syn deleted file mode 100644 index 06b6554..0000000 --- a/sw/cpld_test/cpld_test.syn +++ /dev/null @@ -1,11 +0,0 @@ -JDF B -// Created by Version 2.0 -PROJECT cpld_test -DESIGN cpld_test Normal -DEVKIT M4A5-32/32-10JC -ENTRY Pure VHDL -MODULE cpld_test.vhd -MODSTYLE cpld_test Normal -SYNTHESIS_TOOL Synplify -SIMULATOR_TOOL ActiveHDL -TOPMODULE cpld_test diff --git a/sw/cpld_test/cpld_test.vhd b/sw/cpld_test/cpld_test.vhd deleted file mode 100644 index b1161e9..0000000 --- a/sw/cpld_test/cpld_test.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -entity cpld_test is - IN_PIN: in std_logic; - OUT_PIN: out std_logic; -end; - -architecture behavioral of cpld_test is -begin - OUT_PIN <= not(IN_PIN); -end behavioral; - diff --git a/sw/cpld_test/cpld_test_tcl.ini b/sw/cpld_test/cpld_test_tcl.ini deleted file mode 100644 index e69de29..0000000 --- a/sw/cpld_test/cpld_test_tcl.ini +++ /dev/null diff --git a/sw/cpld_test/run_options.txt b/sw/cpld_test/run_options.txt deleted file mode 100644 index e4fea81..0000000 --- a/sw/cpld_test/run_options.txt +++ /dev/null @@ -1,56 +0,0 @@ -#-- Synopsys, Inc. -#-- Version I-2014.03LC -#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\run_options.txt -#-- Written on Thu Jun 01 13:51:51 2017 - - -#project files -add_file -vhdl -lib work "./cpld_test.vhd" - - - -#implementation: "cpld_test" -impl -add cpld_test -type fpga - -#device options -set_option -technology mach -set_option -part M4A5-32 -set_option -package "" -set_option -speed_grade "" -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "cpld_test" - -# mapper_options -set_option -frequency 1 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -srs_instrumentation 1 - -# Lattice ispMACH4000 -set_option -maxfanin 20 -set_option -RWCheckOnRam 1 -set_option -maxterms 16 -set_option -areadelay 0 -set_option -disable_io_insertion 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./cpld_test.edi" - -#set log file -set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" -impl -active "cpld_test" diff --git a/sw/cpld_test/scratchproject.prs b/sw/cpld_test/scratchproject.prs deleted file mode 100644 index 9db3bb5..0000000 --- a/sw/cpld_test/scratchproject.prs +++ /dev/null @@ -1,54 +0,0 @@ -#-- Synopsys, Inc. -#-- Version I-2014.03LC -#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\scratchproject.prs - -#project files -add_file -vhdl -lib work "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.vhd" - - - -#implementation: "cpld_test" -impl -add \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test -type fpga - -#device options -set_option -technology mach -set_option -part M4A5-32 -set_option -package "" -set_option -speed_grade "" -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "cpld_test" - -# mapper_options -set_option -frequency 1 -set_option -write_verilog 0 -set_option -write_vhdl 0 -set_option -srs_instrumentation 1 - -# Lattice ispMACH4000 -set_option -maxfanin 20 -set_option -RWCheckOnRam 1 -set_option -maxterms 16 -set_option -areadelay 0 -set_option -disable_io_insertion 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi" - -#set log file -set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" -impl -active "cpld_test" diff --git a/sw/cpld_test/stdout.log b/sw/cpld_test/stdout.log deleted file mode 100644 index 968f5e3..0000000 --- a/sw/cpld_test/stdout.log +++ /dev/null @@ -1,35 +0,0 @@ -Running in Lattice mode - - -Starting: C:\ispLEVER_Classic2\synpbase\bin\mbin\synbatch.exe -Install: C:\ispLEVER_Classic2\synpbase -Date: Thu Jun 01 13:51:51 2017 -Version: I-2014.03LC - -Arguments: -product synplify_pro -batch //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj -ProductType: synplify_pro - - - - - -log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" - -Running cpld_test|cpld_test - -Running: Compile on cpld_test|cpld_test - -Running: Compile Process on cpld_test|cpld_test - -Running: Compile Input on cpld_test|cpld_test -compiler exited with errors -Job: "compiler" terminated with error status: 2. -See log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" -Return Code: 2 -Run Time:0h:00m:00s -Copied \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr to \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srf - -exit status=2 - -exit status=2 - diff --git a/sw/cpld_test/synlog.tcl b/sw/cpld_test/synlog.tcl deleted file mode 100644 index 403d18e..0000000 --- a/sw/cpld_test/synlog.tcl +++ /dev/null @@ -1 +0,0 @@ -project -load //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.prj diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt deleted file mode 100644 index fb62f97..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt +++ /dev/null @@ -1,4 +0,0 @@ -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -@E|Parse errors encountered - exiting - diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt deleted file mode 100644 index 6c7370d..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt +++ /dev/null @@ -1,3 +0,0 @@ -@N|Running in 32-bit mode -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns - diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml b/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml deleted file mode 100644 index 937182a..0000000 --- a/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" ?> -<!-- ************************************************************************************* -FILE DESCRIPTION -The file contains the job information from compiler to be displayed as part of the summary report. -*******************************************************************************************--> - -<job_run_status name="compiler"> - <report_link name="Detailed report"> - <data>\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr</data> - <title>Start of Compile</title> - </report_link> - <job_status> - <data>Failed </data> - </job_status> -<job_info> - <info name="Notes"> - <data>2</data> - <report_link name="more"><data>\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_notes.txt</data></report_link> - </info> - <info name="Warnings"> - <data>0</data> - <report_link name="more"><data>\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_warnings.txt</data></report_link> - </info> - <info name="Errors"> - <data>3</data> - <report_link name="more"><data>\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_errors.txt</data></report_link> - </info> - <info name="CPU Time"> - <data>-</data> - </info> - <info name="Real Time"> - <data>0h:00m:00s</data> - </info> - <info name="Peak Memory"> - <data>-</data> - </info> - <info name="Date &Time"> - <data type="timestamp">1496317911</data> - </info> - </job_info> -</job_run_status>
\ No newline at end of file diff --git a/sw/cpld_test/syntmp/closed.png b/sw/cpld_test/syntmp/closed.png Binary files differdeleted file mode 100644 index 0d78634..0000000 --- a/sw/cpld_test/syntmp/closed.png +++ /dev/null diff --git a/sw/cpld_test/syntmp/cmdrec_compiler.log b/sw/cpld_test/syntmp/cmdrec_compiler.log deleted file mode 100644 index 24cfe61..0000000 --- a/sw/cpld_test/syntmp/cmdrec_compiler.log +++ /dev/null @@ -1,7 +0,0 @@ -C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe -osyn \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs -top cpld_test -prodtype synplify_pro -nostructver -dfltencoding sequential -encrypt -pro -dmgen \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -loga \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr -rc:2 success:0 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs|o|0|0 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd|i|1496311903|284 -\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr|o|1496317911|1349 -C:\ispLEVER_Classic2\synpbase\bin64\c_vhdl.exe|i|1401224104|5533184 -C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe|i|1401223898|2046976 diff --git a/sw/cpld_test/syntmp/cpld_test_srr.htm b/sw/cpld_test/syntmp/cpld_test_srr.htm deleted file mode 100644 index a234dd1..0000000 --- a/sw/cpld_test/syntmp/cpld_test_srr.htm +++ /dev/null @@ -1,29 +0,0 @@ -<html><body><samp><pre> -<!@TC:1496317911> -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -<a name=compilerReport1>$ Start of Compile</a> -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N: : <!@TM:1496317911> | Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1496317911> | Setting time resolution to ns -Top entity isn't set yet! -<a name=error2><font color=red>@E:<a href="@E:CD169:@XP_HELP">CD169</a> : <a href="\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd:7:1:7:7:@E:CD169:@XP_MSG">cpld_test.vhd(7)</a><!@TM:1496317911> | Illegal declaration</font> -<a name=error3><font color=red>@E:<a href="@E:CD213:@XP_HELP">CD213</a> : <a href="\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd:13:1:13:8:@E:CD213:@XP_MSG">cpld_test.vhd(13)</a><!@TM:1496317911> | Undefined identifier</font> -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -<a name=error4><font color=red>@E: : <!@TM:1496317911> | Parse errors encountered - exiting</font> -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] - -</pre></samp></body></html> diff --git a/sw/cpld_test/syntmp/cpld_test_toc.htm b/sw/cpld_test/syntmp/cpld_test_toc.htm deleted file mode 100644 index 6e8aa83..0000000 --- a/sw/cpld_test/syntmp/cpld_test_toc.htm +++ /dev/null @@ -1,25 +0,0 @@ - <html> - <head> - <script type="text/javascript" src="file:///C:\ispLEVER_Classic2\synpbase\lib\report\reportlog_tree.js"></script> - <link rel="stylesheet" type="text/css" href="file:///C:\ispLEVER_Classic2\synpbase\lib\report\reportlog_tree.css" /> - </head> - - <body style="background-color:#e0e0ff;"> - <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script> - <ul id="cpld_test-menu" class="treeview" style="padding-left:12;"> - <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">cpld_test (cpld_test)</b> - <ul rel="open" style="font-size:small;"> - -<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b> -<ul rel="open"> -<li><a href="file:///\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\syntmp\cpld_test_srr.htm#error2" target="srrFrame" title="">Error in report!</a> </li> -<li><a href="file:///\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\syntmp\cpld_test_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li></ul></li> -<li><a href="file:///\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\stdout.log" target="srrFrame" title="">Session Log (13:50 01-Jun)</a> -<ul ></ul></li> </ul> - </li> - </ul> - - <script type="text/javascript"> reportLogObj.generateLog("cpld_test-menu")</script> - - </body> - </html>
\ No newline at end of file diff --git a/sw/cpld_test/syntmp/open.png b/sw/cpld_test/syntmp/open.png Binary files differdeleted file mode 100644 index a227005..0000000 --- a/sw/cpld_test/syntmp/open.png +++ /dev/null diff --git a/sw/cpld_test/syntmp/run_option.xml b/sw/cpld_test/syntmp/run_option.xml deleted file mode 100644 index 365c522..0000000 --- a/sw/cpld_test/syntmp/run_option.xml +++ /dev/null @@ -1,18 +0,0 @@ -<?xml version="1.0" encoding="utf-8"?> -<!-- - Synopsys, Inc. - Version I-2014.03LC - Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\syntmp\run_option.xml - Written on Thu Jun 01 13:51:51 2017 - - ---> -<project_attribute_list name="Project Settings"> - <option name="project_name" display_name="Project Name">cpld_test</option> - <option name="impl_name" display_name="Implementation Name">cpld_test</option> - <option name="top_module" display_name="Top Module">cpld_test</option> - <option name="resource_sharing" display_name="Resource Sharing">1</option> - <option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option> - <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option> -</project_attribute_list> - diff --git a/sw/cpld_test/syntmp/statusReport.html b/sw/cpld_test/syntmp/statusReport.html deleted file mode 100644 index 1914c86..0000000 --- a/sw/cpld_test/syntmp/statusReport.html +++ /dev/null @@ -1,49 +0,0 @@ -<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> - <html xmlns="http://www.w3.org/1999/xhtml"> - <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" /> - <title>Project Status Summary Page</title> - <script type="text/javascript" src="projectstatuspage.js"></script> - <link rel="stylesheet" type="text/css" href="projectstatuspage.css" /> - </head> - - <body style="background-color:#f0f0ff;"> - -<table style="border:none;" width="100%" ><tr> <td class="outline"> -<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead><tr><th colspan="4">Project Settings</th><tr> - <tr> <td class="optionTitle" align="left"> Project Name</td> <td> cpld_test</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> cpld_test</td> </tr> - </thead> - <tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> cpld_test</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr> -<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr> - -</tbody> - </table><br> <table width="100%" border="0" cellspacing= "0" cellpadding= "0"> - <thead><tr><th colspan="9">Run Status</th></tr></thead> - <tbody> - <tr> - <th align="left" width="17%">Job Name</th> - <th align="left">Status</th> - <td class="lnote" align="center" title="Notes"></td> - <td class="lwarn" align="center" title="Warnings"></td> - <td class="lerror" align="center" title="Errors"></td> - <th align="left">CPU Time</th> - <th align="left">Real Time</th> - <th align="left">Memory</th> - <th align="left">Date/Time</th> - </tr> - <tr> - <td class="optionTitle">Compile Input</td><td>Error</td> - <td>2</td> -<td>0</td> - <td style="background-color:#FFBBBB;">3</td> -<td>-</td> -<td>0m:00s</td> -<td>-</td> -<td><font size="-1">01.06.2017</font><br/><font size="-2">13:51:51</font></td> -</tr> - -<tr> - <td class="optionTitle">Map & Optimize</td> - <td>out-of-date</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1"></font><br/><font size="-2"></font></td> </tbody> - </table> - </td></tr></table></body> - </html>
\ No newline at end of file diff --git a/sw/cpld_test/synwork/cpld_test_comp.fdeporig b/sw/cpld_test/synwork/cpld_test_comp.fdeporig deleted file mode 100644 index b63dfe0..0000000 --- a/sw/cpld_test/synwork/cpld_test_comp.fdeporig +++ /dev/null @@ -1,22 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-top|cpld_test|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\bin\\c_vhdl.exe":1401223898 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\location.map":1310457374 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std1164.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\numeric.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\arith.vhd":1401223722 -#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722 -#CUR:"\\\\nas001\\account_pif\\_prossn\\samb_3\\lab3\\projects\\z80upc\\sw\\cpld_test\\cpld_test.vhd":1496311903 -0 "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 - -# Dependency Lists (Users Of) -0 -1 - -# Design Unit to File Association -arch work cpld_test behavioral 0 |
