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Diffstat (limited to 'sw/cpld_test/automake.log')
| -rw-r--r-- | sw/cpld_test/automake.log | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/sw/cpld_test/automake.log b/sw/cpld_test/automake.log deleted file mode 100644 index f33bc75..0000000 --- a/sw/cpld_test/automake.log +++ /dev/null @@ -1,41 +0,0 @@ -ispLEVER Auto-Make Log File ---------------------------- - -Updating: Pre-Fit Equations - -Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\Synpwrap.exe -e cpld_test -target mach -pro ' - -Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. -Version : 2.0.00.17.20.15 - -Done sucessfully with exit code 2. -#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLEVER_Classic2\synpbase -#OS: Windows 7 6.1 -#Hostname: PC805012 - -#Implementation: cpld_test - -$ Start of Compile -#Thu Jun 01 13:51:51 2017 - -Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 -@N|Running in 32-bit mode -Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. - -@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -Top entity isn't set yet! -@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration -@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier -2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -@END -@E|Parse errors encountered - exiting -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jun 01 13:51:51 2017 - -###########################################################] - -Error output EDIF file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi -Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 - -Done: failed with exit code: 0002. |