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+JDF B
+// Created by Version 2.0
+PROJECT cpld_test
+DESIGN cpld_test Normal
+DEVKIT M4A5-32/32-10JC
+ENTRY Pure VHDL
+MODULE cpld_test.vhd
+MODSTYLE cpld_test Normal
+SYNTHESIS_TOOL Synplify
+SIMULATOR_TOOL ActiveHDL
+TOPMODULE cpld_test