1 files changed, 169 insertions, 0 deletions
diff --git a/sw/pld/ADDRESS_DECODER.pdf b/sw/pld/ADDRESS_DECODER.pdf
new file mode 100644
index 0000000..2a0c7dc
--- /dev/null
+++ b/sw/pld/ADDRESS_DECODER.pdf
@@ -0,0 +1,169 @@
+{COMPONENT F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER.SYM
+
+ {ENVIRONMENT
+  {PDIFvrev 3.00}
+  {Program "CUPL(WM) Version 5.0a"}
+  {DBtype "Schematic"}
+  {DBvrev 1.01}
+  {DBtime "Fri Mar 17 15:18:30 2017 "}
+  {DBunit "MIL"}
+  {DBgrid 10}
+  {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 
+          "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 
+          "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 
+          "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+  {VIEW
+   {Mode SYMB}
+   {Nlst OPEN}
+   {Vw 0 0 2}
+   {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+   {Gs 10 10}
+  }
+ }
+
+ {DISPLAY
+  [Ly "PINNUM"]
+  [Ls "SOLID"][Wd 0]
+  [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+  {PIN_DEF
+   [Ly "PINCON"]
+   {P A8 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+   {P A9 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+   {P A10 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+   {P A11 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+   {P A12 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+   {P A13 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+   {P A14 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+   {P A15 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+   {P CSROML {Pt "I/O"}{Lq 0}{Ploc 290 20}}
+   {P CSROMH {Pt "I/O"}{Lq 0}{Ploc 290 40}}
+   {P CSRAM {Pt "I/O"}{Lq 0}{Ploc 290 60}}
+   {P CSUART {Pt "I/O"}{Lq 0}{Ploc 290 80}}
+   {P CSCTC {Pt "I/O"}{Lq 0}{Ploc 290 100}}
+   {P CSPIO {Pt "I/O"}{Lq 0}{Ploc 290 120}}
+  }
+
+  {PKG
+   [Ly "REFDES"]
+   [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+   {Rdl 195 190}
+
+   [Ly "PINNUM"]
+   [Ts 15][Tj "RC"]
+   {Pnl 120 170}
+   {Pnl 120 150}
+   {Pnl 120 130}
+   {Pnl 120 110}
+   {Pnl 120 90}
+   {Pnl 120 70}
+   {Pnl 120 50}
+   {Pnl 120 30}
+   [Ts 15][Tj "LC"]
+   {Pnl 270 30}
+   {Pnl 270 50}
+   {Pnl 270 70}
+   {Pnl 270 90}
+   {Pnl 270 110}
+   {Pnl 270 130}
+
+   {Sd A 2 3 4 5 6 7 8 9 12 13 14 15 16 17}
+  }
+
+  {PIC
+   [Ly "GATE"]
+   [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+   {R 130 180 260 0}
+   {L 130 160 100 160}
+   {L 130 140 100 140}
+   {L 130 120 100 120}
+   {L 130 100 100 100}
+   {L 130 80 100 80}
+   {L 130 60 100 60}
+   {L 130 40 100 40}
+   {L 130 20 100 20}
+   {L 260 20 290 20}
+   {L 260 40 290 40}
+   {L 260 60 290 60}
+   {L 260 80 290 80}
+   {L 260 100 290 100}
+   {L 260 120 290 120}
+   [Ly "PINNAM"]
+   [Tj "LC"]
+   {T "A8" 140 160}
+   {T "A9" 140 140}
+   {T "A10" 140 120}
+   {T "A11" 140 100}
+   {T "A12" 140 80}
+   {T "A13" 140 60}
+   {T "A14" 140 40}
+   {T "A15" 140 20}
+   [Tj "RC"]
+   {T "CSROML" 250 20}
+   {T "CSROMH" 250 40}
+   {T "CSRAM" 250 60}
+   {T "CSUART" 250 80}
+   {T "CSCTC" 250 100}
+   {T "CSPIO" 250 120}
+   [Ly "DEVICE"]
+   [Tj "CT"]
+   {T "G16V8AS" 195 -10}
+  }
+
+  {ATR
+   {IN
+    {Org 100 20}
+    {Ty 255}
+   }
+   {EX
+    [Ly "ATTR2"]
+    [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+    {At PLD F:\SCHOOL\LAB3\PROJECTS\Z80UPC\SW\PLD\ADDRESS_DECODER 195 180}
+   }
+  }
+ }
+
+ {DETAIL
+  {ANNOTATE
+  }
+
+  {NET_DEF
+   {N A8
+   }
+   {N A9
+   }
+   {N A10
+   }
+   {N A11
+   }
+   {N A12
+   }
+   {N A13
+   }
+   {N A14
+   }
+   {N A15
+   }
+   {N CSROML
+   }
+   {N CSROMH
+   }
+   {N CSRAM
+   }
+   {N CSUART
+   }
+   {N CSCTC
+   }
+   {N CSPIO
+   }
+  }
+
+  {SUBCOMP
+  }
+ }
+}