summaryrefslogtreecommitdiffstats
path: root/hw/History (unfollow)
Commit message (Expand)AuthorFilesLines
2017-05-19finish wiring and add eurocard compliant standard holesNao Pross161-0/+0
2017-05-19wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross50-0/+0
2017-05-18new traces for cpu signals and for high address to the MMU / addr decoderNao Pross25-0/+0
2017-05-18wiring for CTC (U8) to address bus and data busNao Pross15-0/+0
2017-05-18wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross4-0/+0
2017-05-18wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross30-0/+0
2017-05-09created new layout (starting over)Nao Pross58-0/+0
2017-05-05complete wiring for serial interface connector and logicNao Pross84-0/+0
2017-05-05add switches datasheets for footprintsNao Pross5-0/+0
2017-04-28start printed circuit board designNao Pross123-0/+0
2017-04-13scheme update and PCB startNao Pross37-0/+0
2017-04-04schematic completeNao Pross112-0/+0
2017-03-31added iospace address decoderNao Pross10-0/+0
2017-03-23changed scheme layoutNao Pross104-0/+0
2017-03-17hardware nearly finishedNao Pross324-0/+0
2017-03-06hw: moved everything to one sheetNao Pross215-0/+0
2017-02-24hw: created library project, doc: added 74LS193 datasheetNao Pross12-0/+0
2017-02-24hw: created sch, doc: added uart datasheetNao Pross1-0/+0
2017-02-14hw: created z80acpu in sch libraryNao Pross10-0/+0
generated by cgit v1.2.1 (git 2.18.0) at 2024-11-11 03:45:55 +0100