summaryrefslogtreecommitdiffstats
path: root/hw/History (follow)
Commit message (Collapse)AuthorAgeFilesLines
* scheme update and PCB startNao Pross2017-04-1337-0/+0
| | | | | | add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes
* schematic completeNao Pross2017-04-04112-0/+0
| | | | | | hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD) change main bus connector with a custom one (intead of PC/104) start building footprint library
* added iospace address decoderNao Pross2017-03-3110-0/+0
|
* changed scheme layoutNao Pross2017-03-23104-0/+0
| | | | | | | | | hw: changed scheme and annotated components doc: added build script for windows sw: added res/ folder with blaster and created jedec document for address decoder pld
* hardware nearly finishedNao Pross2017-03-17324-0/+0
| | | | | | | | | | | | | doc: added datasheets for - GAL16V8 - MAX214 - MAX232 added script to build doc under windows with miktex updated notes hw: finished i/o devices and bus viewer sw: created files for pld programming
* hw: moved everything to one sheetNao Pross2017-03-06215-0/+0
|
* hw: created library project, doc: added 74LS193 datasheetNao Pross2017-02-2412-0/+0
|
* hw: created sch, doc: added uart datasheetNao Pross2017-02-241-0/+0
|
* hw: created z80acpu in sch libraryNao Pross2017-02-1410-0/+0
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-29 01:51:53 +0100