summaryrefslogtreecommitdiffstats
path: root/hw/MainBoard.PcbDoc (follow)
Commit message (Expand)AuthorAgeFilesLines
* finish wiring and add eurocard compliant standard holesNao Pross2017-05-191-0/+0
* wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2017-05-191-0/+0
* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-181-0/+0
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-181-0/+0
* wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross2017-05-181-0/+0
* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-181-0/+0
* created new layout (starting over)Nao Pross2017-05-091-0/+0
* complete wiring for serial interface connector and logicNao Pross2017-05-051-0/+0
* add switches datasheets for footprintsNao Pross2017-05-051-0/+0
* start printed circuit board designNao Pross2017-04-281-0/+0
* scheme update and PCB startNao Pross2017-04-131-0/+0