| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
| |
this is probably the last commit before printing the PCB, unless there are some
other errors in the board design
|
| |
|
|
|
|
| |
since there wasn't enough space (I should have added the holes before
beginning) there are only 4 holes instead of 6 (2 will be cut out
since the space is unused).
|
| | |
|
| |
|
|
| |
the old layout is still under hw/MainBoard1.PcbDoc
|
| |
|
|
|
|
|
| |
other changes:
- new layout, probably the board will have to be resized to a
nonstandard size (currently 2EUROCARD)
- new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors
|
| |
|
|
|
|
|
|
|
| |
wired:
- clock circiuts
- reset button
set layout for:
- CPU & memory
- serial interface
|
| |
|
|
|
|
| |
add missing capacitor and resistor values (serial XTAL)
create new eurocard standard compliant PCB for the uPC
and other minor fixes
|
| |
|
|
|
|
| |
hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD)
change main bus connector with a custom one (intead of PC/104)
start building footprint library
|
| |
|
|
|
|
|
|
|
| |
hw: changed scheme and annotated components
doc: added build script for windows
sw: added res/ folder with blaster and created jedec document for
address decoder pld
|
|
|
doc: added datasheets for
- GAL16V8
- MAX214
- MAX232
added script to build doc under windows with miktex
updated notes
hw: finished i/o devices and bus viewer
sw: created files for pld programming
|
