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* wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2017-05-191-3/+3
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* new traces for cpu signals and for high address to the MMU / addr decoderNao Pross2017-05-181-3/+3
| | | | there are also many other minor changes to connect various wires
* wiring for CTC (U8) to address bus and data busNao Pross2017-05-181-3/+3
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* wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2017-05-181-3/+3
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* created new layout (starting over)Nao Pross2017-05-091-3/+3
| | | | the old layout is still under hw/MainBoard1.PcbDoc
* complete wiring for serial interface connector and logicNao Pross2017-05-051-3/+3
| | | | | | | other changes: - new layout, probably the board will have to be resized to a nonstandard size (currently 2EUROCARD) - new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors
* add switches datasheets for footprintsNao Pross2017-05-051-3/+3
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* start printed circuit board designNao Pross2017-04-281-12/+12
| | | | | | | | | wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface
* scheme update and PCB startNao Pross2017-04-131-0/+14
add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes