summaryrefslogtreecommitdiffstats
path: root/hw/__Previews (unfollow)
Commit message (Collapse)AuthorFilesLines
2018-10-30Move sw to sw-old and hw to hw-altium, add kicad filesNao Pross9-126/+0
2017-11-28Add datasheets and resourcesNao Pross1-3/+3
2017-05-23board complete, generate gerber (x2) fileshardwareNao Pross5-21/+21
this is probably the last commit before printing the PCB, unless there are some other errors in the board design
2017-05-19finish wiring and add eurocard compliant standard holesNao Pross4-12/+12
since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused).
2017-05-19wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2-6/+6
2017-05-18new traces for cpu signals and for high address to the MMU / addr decoderNao Pross1-3/+3
there are also many other minor changes to connect various wires
2017-05-18wiring for CTC (U8) to address bus and data busNao Pross1-3/+3
2017-05-18wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross1-3/+3
2017-05-18wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2-6/+6
2017-05-09created new layout (starting over)Nao Pross6-15/+29
the old layout is still under hw/MainBoard1.PcbDoc
2017-05-05complete wiring for serial interface connector and logicNao Pross5-15/+15
other changes: - new layout, probably the board will have to be resized to a nonstandard size (currently 2EUROCARD) - new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors
2017-05-05add switches datasheets for footprintsNao Pross5-15/+15
2017-04-28start printed circuit board designNao Pross5-24/+24
wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface
2017-04-13scheme update and PCB startNao Pross5-12/+26
add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes
2017-04-04schematic completeNao Pross6-12/+40
hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD) change main bus connector with a custom one (intead of PC/104) start building footprint library
2017-03-31added iospace address decoderNao Pross4-12/+12
2017-03-23changed scheme layoutNao Pross4-12/+12
hw: changed scheme and annotated components doc: added build script for windows sw: added res/ folder with blaster and created jedec document for address decoder pld
2017-03-17hardware nearly finishedNao Pross5-12/+54
doc: added datasheets for - GAL16V8 - MAX214 - MAX232 added script to build doc under windows with miktex updated notes hw: finished i/o devices and bus viewer sw: created files for pld programming
2017-03-06hw: moved everything to one sheetNao Pross2-9/+23
2017-03-05doc: added L7805ACV datasheet; hw: updated schemeNao Pross1-3/+3
2017-02-24hw: created library project, doc: added 74LS193 datasheetNao Pross1-3/+3
2017-02-24hw: created sch, doc: added uart datasheetNao Pross1-0/+14