summaryrefslogtreecommitdiffstats
path: root/hw/__Previews (unfollow)
Commit message (Expand)AuthorFilesLines
2017-05-19wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross2-6/+6
2017-05-18new traces for cpu signals and for high address to the MMU / addr decoderNao Pross1-3/+3
2017-05-18wiring for CTC (U8) to address bus and data busNao Pross1-3/+3
2017-05-18wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross1-3/+3
2017-05-18wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross2-6/+6
2017-05-09created new layout (starting over)Nao Pross6-15/+29
2017-05-05complete wiring for serial interface connector and logicNao Pross5-15/+15
2017-05-05add switches datasheets for footprintsNao Pross5-15/+15
2017-04-28start printed circuit board designNao Pross5-24/+24
2017-04-13scheme update and PCB startNao Pross5-12/+26
2017-04-04schematic completeNao Pross6-12/+40
2017-03-31added iospace address decoderNao Pross4-12/+12
2017-03-23changed scheme layoutNao Pross4-12/+12
2017-03-17hardware nearly finishedNao Pross5-12/+54
2017-03-06hw: moved everything to one sheetNao Pross2-9/+23
2017-03-05doc: added L7805ACV datasheet; hw: updated schemeNao Pross1-3/+3
2017-02-24hw: created library project, doc: added 74LS193 datasheetNao Pross1-3/+3
2017-02-24hw: created sch, doc: added uart datasheetNao Pross1-0/+14
generated by cgit v1.2.1 (git 2.18.0) at 2024-12-23 11:12:00 +0100