Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Move sw to sw-old and hw to hw-altium, add kicad files | Nao Pross | 2018-10-30 | 9 | -126/+0 |
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* | Add datasheets and resources | Nao Pross | 2017-11-28 | 1 | -3/+3 |
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* | board complete, generate gerber (x2) fileshardware | Nao Pross | 2017-05-23 | 5 | -21/+21 |
| | | | | | this is probably the last commit before printing the PCB, unless there are some other errors in the board design | ||||
* | finish wiring and add eurocard compliant standard holes | Nao Pross | 2017-05-19 | 4 | -12/+12 |
| | | | | | | since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused). | ||||
* | wiring for 7 segment displays and traces for the remaining CPU signals | Nao Pross | 2017-05-19 | 2 | -6/+6 |
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* | new traces for cpu signals and for high address to the MMU / addr decoder | Nao Pross | 2017-05-18 | 1 | -3/+3 |
| | | | | there are also many other minor changes to connect various wires | ||||
* | wiring for CTC (U8) to address bus and data bus | Nao Pross | 2017-05-18 | 1 | -3/+3 |
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* | wiring for P4 and P5 (I/O ports) and circuits for CLKs and RST | Nao Pross | 2017-05-18 | 1 | -3/+3 |
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* | wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550 | Nao Pross | 2017-05-18 | 2 | -6/+6 |
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* | created new layout (starting over) | Nao Pross | 2017-05-09 | 6 | -15/+29 |
| | | | | the old layout is still under hw/MainBoard1.PcbDoc | ||||
* | complete wiring for serial interface connector and logic | Nao Pross | 2017-05-05 | 5 | -15/+15 |
| | | | | | | | other changes: - new layout, probably the board will have to be resized to a nonstandard size (currently 2EUROCARD) - new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors | ||||
* | add switches datasheets for footprints | Nao Pross | 2017-05-05 | 5 | -15/+15 |
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* | start printed circuit board design | Nao Pross | 2017-04-28 | 5 | -24/+24 |
| | | | | | | | | | wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface | ||||
* | scheme update and PCB start | Nao Pross | 2017-04-13 | 5 | -12/+26 |
| | | | | | | add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes | ||||
* | schematic complete | Nao Pross | 2017-04-04 | 6 | -12/+40 |
| | | | | | | hw: change address decoder chip from GAL16V8 to M4-32/32 (CPLD) change main bus connector with a custom one (intead of PC/104) start building footprint library | ||||
* | added iospace address decoder | Nao Pross | 2017-03-31 | 4 | -12/+12 |
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* | changed scheme layout | Nao Pross | 2017-03-23 | 4 | -12/+12 |
| | | | | | | | | | hw: changed scheme and annotated components doc: added build script for windows sw: added res/ folder with blaster and created jedec document for address decoder pld | ||||
* | hardware nearly finished | Nao Pross | 2017-03-17 | 5 | -12/+54 |
| | | | | | | | | | | | | | doc: added datasheets for - GAL16V8 - MAX214 - MAX232 added script to build doc under windows with miktex updated notes hw: finished i/o devices and bus viewer sw: created files for pld programming | ||||
* | hw: moved everything to one sheet | Nao Pross | 2017-03-06 | 2 | -9/+23 |
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* | doc: added L7805ACV datasheet; hw: updated scheme | Nao Pross | 2017-03-05 | 1 | -3/+3 |
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* | hw: created library project, doc: added 74LS193 datasheet | Nao Pross | 2017-02-24 | 1 | -3/+3 |
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* | hw: created sch, doc: added uart datasheet | Nao Pross | 2017-02-24 | 1 | -0/+14 |