summaryrefslogtreecommitdiffstats
path: root/hw (unfollow)
Commit message (Expand)AuthorFilesLines
2017-05-19finish wiring and add eurocard compliant standard holesNao Pross178-55/+790
2017-05-19wiring for 7 segment displays and traces for the remaining CPU signalsNao Pross54-6/+56
2017-05-18new traces for cpu signals and for high address to the MMU / addr decoderNao Pross27-3/+3
2017-05-18wiring for CTC (U8) to address bus and data busNao Pross17-3/+3
2017-05-18wiring for P4 and P5 (I/O ports) and circuits for CLKs and RSTNao Pross6-3/+3
2017-05-18wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550Nao Pross33-6/+6
2017-05-09created new layout (starting over)Nao Pross73-130/+1039
2017-05-05complete wiring for serial interface connector and logicNao Pross97-15/+20
2017-05-05add switches datasheets for footprintsNao Pross13-17/+17
2017-04-28start printed circuit board designNao Pross158-31/+11374
2017-04-13scheme update and PCB startNao Pross51-109/+1787
2017-04-04schematic completeNao Pross131-98/+214
2017-03-31added iospace address decoderNao Pross17-12/+12
2017-03-23changed scheme layoutNao Pross119-13/+189
2017-03-17hardware nearly finishedNao Pross339-125/+850
2017-03-06hw: moved everything to one sheetNao Pross226-57/+662
2017-03-05doc: added L7805ACV datasheet; hw: updated schemeNao Pross6-13/+1275
2017-02-24hw: created library project, doc: added 74LS193 datasheetNao Pross17-464/+5
2017-02-24hw: created sch, doc: added uart datasheetNao Pross5-3/+501
2017-02-14hw: created z80acpu in sch libraryNao Pross12-0/+1005
generated by cgit v1.2.1 (git 2.18.0) at 2024-11-19 00:46:47 +0100