From 6105426e159a55cfb15fee3e999bb4fcf6289446 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 16 Jun 2017 15:25:54 +0200 Subject: new components list and cpld test unit --- doc/components_list.ods | Bin 0 -> 16030 bytes doc/components_list.pdf | Bin 0 -> 32648 bytes sw/cpld/automake.log | 6 +- sw/cpld/syndos.env | 41 -------- sw/cpld_test/.tmp_log | 0 sw/cpld_test/automake.log | 41 ++++++++ sw/cpld_test/cpld_test.STY | 22 ++++ sw/cpld_test/cpld_test.htm | 9 ++ sw/cpld_test/cpld_test.jhd | 3 + sw/cpld_test/cpld_test.jid | 1 + sw/cpld_test/cpld_test.lci | 63 ++++++++++++ sw/cpld_test/cpld_test.lct | 63 ++++++++++++ sw/cpld_test/cpld_test.lct.bak | 113 +++++++++++++++++++++ sw/cpld_test/cpld_test.naf | 0 sw/cpld_test/cpld_test.prj | 34 +++++++ sw/cpld_test/cpld_test.rev | 3 + sw/cpld_test/cpld_test.srf | 25 +++++ sw/cpld_test/cpld_test.srr | 25 +++++ sw/cpld_test/cpld_test.syn | 11 ++ sw/cpld_test/cpld_test.vhd | 15 +++ sw/cpld_test/cpld_test_tcl.ini | 0 sw/cpld_test/run_options.txt | 56 ++++++++++ sw/cpld_test/scratchproject.prs | 54 ++++++++++ sw/cpld_test/stdout.log | 35 +++++++ sw/cpld_test/synlog.tcl | 1 + .../synlog/report/cpld_test_compiler_errors.txt | 4 + .../synlog/report/cpld_test_compiler_notes.txt | 3 + .../synlog/report/cpld_test_compiler_runstatus.xml | 41 ++++++++ sw/cpld_test/syntmp/closed.png | Bin 0 -> 3672 bytes sw/cpld_test/syntmp/cmdrec_compiler.log | 7 ++ sw/cpld_test/syntmp/cpld_test_srr.htm | 29 ++++++ sw/cpld_test/syntmp/cpld_test_toc.htm | 25 +++++ sw/cpld_test/syntmp/open.png | Bin 0 -> 452 bytes sw/cpld_test/syntmp/run_option.xml | 18 ++++ sw/cpld_test/syntmp/statusReport.html | 49 +++++++++ sw/cpld_test/synwork/cpld_test_comp.fdeporig | 22 ++++ 36 files changed, 773 insertions(+), 46 deletions(-) create mode 100644 doc/components_list.ods create mode 100644 doc/components_list.pdf delete mode 100644 sw/cpld/syndos.env create mode 100644 sw/cpld_test/.tmp_log create mode 100644 sw/cpld_test/automake.log create mode 100644 sw/cpld_test/cpld_test.STY create mode 100644 sw/cpld_test/cpld_test.htm create mode 100644 sw/cpld_test/cpld_test.jhd create mode 100644 sw/cpld_test/cpld_test.jid create mode 100644 sw/cpld_test/cpld_test.lci create mode 100644 sw/cpld_test/cpld_test.lct create mode 100644 sw/cpld_test/cpld_test.lct.bak create mode 100644 sw/cpld_test/cpld_test.naf create mode 100644 sw/cpld_test/cpld_test.prj create mode 100644 sw/cpld_test/cpld_test.rev create mode 100644 sw/cpld_test/cpld_test.srf create mode 100644 sw/cpld_test/cpld_test.srr create mode 100644 sw/cpld_test/cpld_test.syn create mode 100644 sw/cpld_test/cpld_test.vhd create mode 100644 sw/cpld_test/cpld_test_tcl.ini create mode 100644 sw/cpld_test/run_options.txt create mode 100644 sw/cpld_test/scratchproject.prs create mode 100644 sw/cpld_test/stdout.log create mode 100644 sw/cpld_test/synlog.tcl create mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt create mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt create mode 100644 sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml create mode 100644 sw/cpld_test/syntmp/closed.png create mode 100644 sw/cpld_test/syntmp/cmdrec_compiler.log create mode 100644 sw/cpld_test/syntmp/cpld_test_srr.htm create mode 100644 sw/cpld_test/syntmp/cpld_test_toc.htm create mode 100644 sw/cpld_test/syntmp/open.png create mode 100644 sw/cpld_test/syntmp/run_option.xml create mode 100644 sw/cpld_test/syntmp/statusReport.html create mode 100644 sw/cpld_test/synwork/cpld_test_comp.fdeporig diff --git a/doc/components_list.ods b/doc/components_list.ods new file mode 100644 index 0000000..9c8f29e Binary files /dev/null and b/doc/components_list.ods differ diff --git a/doc/components_list.pdf b/doc/components_list.pdf new file mode 100644 index 0000000..6ad8a29 Binary files /dev/null and b/doc/components_list.pdf differ diff --git a/sw/cpld/automake.log b/sw/cpld/automake.log index f24e14f..700da07 100644 --- a/sw/cpld/automake.log +++ b/sw/cpld/automake.log @@ -1,10 +1,6 @@ ispLEVER Auto-Make Log File --------------------------- -Updating: Hierarchy -Start to record tcl script... -Finished recording TCL script. - -Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\vhd2jhd.exe address_decoder.vhd -o address_decoder.jhd -m "C:\ispLEVER_Classic2\ispcpld/generic/lib/vhd/location.map" -p "C:\ispLEVER_Classic2\ispcpld/generic/lib"' +Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\checkini.exe -err=automake.err "C:\ispLEVER_Classic2\ispcpld\config\lc.ini"' Done: completed successfully. diff --git a/sw/cpld/syndos.env b/sw/cpld/syndos.env deleted file mode 100644 index 16036da..0000000 --- a/sw/cpld/syndos.env +++ /dev/null @@ -1,41 +0,0 @@ -ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5 -DIOEDA_ABEL5DEV=C:\ispLEVER_Classic2\ispcpld\lib5 -DIOEDA_ActiveHDL=C:\ispLEVER_Classic2\active-hdl\BIN -DIOEDA_ActiveHDLPath=C:\ispLEVER_Classic2\active-hdl\BIN -DIOEDA_AppNotes=C:\ispLEVER_Classic2\ispcpld\bin -DIOEDA_Bin=C:\ispLEVER_Classic2\ispcpld\bin -DIOEDA_Config=C:\ispLEVER_Classic2\ispcpld\config -DIOEDA_CONTEXT=ispLEVER CLASSIC -DIOEDA_DSPPATH=C:\ispLEVER_Classic2\ispLeverDSP -DIOEDA_EPICPATH=C:\ispLEVER_Classic2\ispfpga\bin\nt -DIOEDA_Examples=C:\ispLEVER_Classic2\examples -DIOEDA_FPGABinPath=C:\ispLEVER_Classic2\ispfpga\bin\nt -DIOEDA_FPGAPath=C:\ispLEVER_Classic2\ispfpga -DIOEDA_HDLExplorer=C:\ispLEVER_Classic2\hdle\win32 -DIOEDA_INI=C:\lsc_env -DIOEDA_ispVM=C:\ispLEVER_Classic2\ispvmsystem -DIOEDA_ispVMSystem=C:\ispLEVER_Classic2\ispvmsystem -DIOEDA_License=C:\ispLEVER_Classic2\license -DIOEDA_LSEPath=C:\ispLEVER_Classic2\lse -DIOEDA_MachPath=C:\ispLEVER_Classic2\ispcpld\bin -DIOEDA_Manuals=C:\ispLEVER_Classic2\ispcpld\manuals -DIOEDA_ModelSim=C:\ispLEVER_Classic2\modelsim\win32loem -DIOEDA_ModelsimPath=C:\ispLEVER_Classic2\modelsim\win32loem -DIOEDA_PDSPath=C:\ispLEVER_Classic2\ispcomp -DIOEDA_Precision=C:\isptools\precision -DIOEDA_PrecisionPath=C:\isptools\precision -DIOEDA_ProductName=ispLEVER -DIOEDA_ProductPrefix=SYN -DIOEDA_ProductTitle=ispLEVER -DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N -DIOEDA_ProductVersion=2.0.00.17 -DIOEDA_ProgramFolder=ispLEVER Classic 2.0 -DIOEDA_Root=C:\ispLEVER_Classic2\ispcpld -DIOEDA_Spectrum=C:\isptools\spectrum -DIOEDA_SpectrumPath=C:\isptools\spectrum -DIOEDA_Synplify=C:\ispLEVER_Classic2\synpbase -DIOEDA_SynplifyPath=C:\ispLEVER_Classic2\synpbase -DIOEDA_Synthesis=C:\ispLEVER_Classic2\lse\bin\nt -DIOEDA_Tutorial=C:\ispLEVER_Classic2\ispcpld\tutorial -DIOPRODUCT=ispLEVER -PATH=C:\ispLEVER_Classic2\ispcpld\bin diff --git a/sw/cpld_test/.tmp_log b/sw/cpld_test/.tmp_log new file mode 100644 index 0000000..e69de29 diff --git a/sw/cpld_test/automake.log b/sw/cpld_test/automake.log new file mode 100644 index 0000000..f33bc75 --- /dev/null +++ b/sw/cpld_test/automake.log @@ -0,0 +1,41 @@ +ispLEVER Auto-Make Log File +--------------------------- + +Updating: Pre-Fit Equations + +Starting: 'C:\ispLEVER_Classic2\ispcpld\bin\Synpwrap.exe -e cpld_test -target mach -pro ' + +Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved. +Version : 2.0.00.17.20.15 + +Done sucessfully with exit code 2. +#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 +#install: C:\ispLEVER_Classic2\synpbase +#OS: Windows 7 6.1 +#Hostname: PC805012 + +#Implementation: cpld_test + +$ Start of Compile +#Thu Jun 01 13:51:51 2017 + +Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 +@N|Running in 32-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +Top entity isn't set yet! +@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration +@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier +2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd +@END +@E|Parse errors encountered - exiting +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Thu Jun 01 13:51:51 2017 + +###########################################################] + +Error output EDIF file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi +Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2 + +Done: failed with exit code: 0002. diff --git a/sw/cpld_test/cpld_test.STY b/sw/cpld_test/cpld_test.STY new file mode 100644 index 0000000..3b3c6ba --- /dev/null +++ b/sw/cpld_test/cpld_test.STY @@ -0,0 +1,22 @@ +[Normal] +synlibXRef=lc4k_pvhd, VHDL.TASKLSVhd, 0, Yes +_EdfFrequency=lc4k_pvhd, VHDL.TASKLSVhd, 0, 200 +_EdfInConsFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, +_EdfSymFSM=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfFanin=lc4k_pvhd, VHDL.TASKLSVhd, 0, 20 +_EdfMaxMacrocell=lc4k_pvhd, VHDL.TASKLSVhd, 0, 16 +_EdfPerDesignOptTiming=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 +_EdfOutputPreFile=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfMapLogic=lc4k_pvhd, VHDL.TASKLSVhd, 0, False +_EdfInsertIO=lc4k_pvhd, VHDL.TASKLSVhd, 0, False +_EdfOutNetForm=lc4k_pvhd, VHDL.TASKLSVhd, 0, None +_EdfNumCritPath=lc4k_pvhd, VHDL.TASKLSVhd, 0, 3 +_EdfUnconsClk=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfNumStartEnd=lc4k_pvhd, VHDL.TASKLSVhd, 0, 0 +_EdfResSharing=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfPushTirstates=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfDefEnumEncode=lc4k_pvhd, VHDL.TASKLSVhd, 0, default +_EdfArrangeVHDLFiles=lc4k_pvhd, VHDL.TASKLSVhd, 0, True +_EdfSynOnOffImp=lc4k_pvhd, VHDL.TASKLSVhd, 0, False +[STRATEGY-LIST] +Normal=True, 1496317751 diff --git a/sw/cpld_test/cpld_test.htm b/sw/cpld_test/cpld_test.htm new file mode 100644 index 0000000..365f96f --- /dev/null +++ b/sw/cpld_test/cpld_test.htm @@ -0,0 +1,9 @@ + + + syntmp/cpld_test_srr.htm log file + + + + + + diff --git a/sw/cpld_test/cpld_test.jhd b/sw/cpld_test/cpld_test.jhd new file mode 100644 index 0000000..9be00a5 --- /dev/null +++ b/sw/cpld_test/cpld_test.jhd @@ -0,0 +1,3 @@ + + +MODULE cpld_test diff --git a/sw/cpld_test/cpld_test.jid b/sw/cpld_test/cpld_test.jid new file mode 100644 index 0000000..c77ab04 --- /dev/null +++ b/sw/cpld_test/cpld_test.jid @@ -0,0 +1 @@ +. cpld_test cpld_test.vhd \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd diff --git a/sw/cpld_test/cpld_test.lci b/sw/cpld_test/cpld_test.lci new file mode 100644 index 0000000..62d7d9d --- /dev/null +++ b/sw/cpld_test/cpld_test.lci @@ -0,0 +1,63 @@ +[Device] +Family=M4A5; +PartNumber=M4A5-32/32-10JC; +Package=44PLCC; +PartType=M4A5-32/32; +Speed=-10; +Operating_condition=COM; +Status=Production; + +[Revision] +Parent=m4a5.lci; +DATE=06/01/2017; +TIME=13:49:11; +Source_Format=Pure_VHDL; +Synthesis=Synplify; + +[Ignore Assignments] + +[Clear Assignments] + +[Backannotate Assignments] + +[Global Constraints] + +[Location Assignments] +Layer = Off; + +[Group Assignments] +Layer = Off; + +[Resource Reservations] +Layer = Off; + +[Fitter Report Format] + +[Power] + +[Source Constraint Option] + +[Fast Bypass] + +[OSM Bypass] + +[Input Registers] + +[Netlist/Delay Format] + +[IO Types] +Layer = off; + +[Pullup] + +[Slewrate] + +[Region] + +[Timing Constraints] + +[HSI Attributes] + +[Input Delay] + + diff --git a/sw/cpld_test/cpld_test.lct b/sw/cpld_test/cpld_test.lct new file mode 100644 index 0000000..62d7d9d --- /dev/null +++ b/sw/cpld_test/cpld_test.lct @@ -0,0 +1,63 @@ +[Device] +Family=M4A5; +PartNumber=M4A5-32/32-10JC; +Package=44PLCC; +PartType=M4A5-32/32; +Speed=-10; +Operating_condition=COM; +Status=Production; + +[Revision] +Parent=m4a5.lci; +DATE=06/01/2017; +TIME=13:49:11; +Source_Format=Pure_VHDL; +Synthesis=Synplify; + +[Ignore Assignments] + +[Clear Assignments] + +[Backannotate Assignments] + +[Global Constraints] + +[Location Assignments] +Layer = Off; + +[Group Assignments] +Layer = Off; + +[Resource Reservations] +Layer = Off; + +[Fitter Report Format] + +[Power] + +[Source Constraint Option] + +[Fast Bypass] + +[OSM Bypass] + +[Input Registers] + +[Netlist/Delay Format] + +[IO Types] +Layer = off; + +[Pullup] + +[Slewrate] + +[Region] + +[Timing Constraints] + +[HSI Attributes] + +[Input Delay] + + diff --git a/sw/cpld_test/cpld_test.lct.bak b/sw/cpld_test/cpld_test.lct.bak new file mode 100644 index 0000000..4bdf950 --- /dev/null +++ b/sw/cpld_test/cpld_test.lct.bak @@ -0,0 +1,113 @@ + +[Device] +Family = lc4k; +PartNumber = LC4064ZE-5UMN64C; +Package = 64ucBGA; +PartType = LC4064ZE; +Speed = -5.8; +Operating_condition = COM; +Status = Production; + +[Revision] +Parent = lc4k64e.lci; +DATE = 2002; +TIME = 0:00:00; +Source_Format = Pure_VHDL; +Synthesis = Synplify; + +[Ignore Assignments] + +[Clear Assignments] + +[Backannotate Assignments] + +[Global Constraints] + +[Location Assignments] +layer = OFF; + +[Group Assignments] +layer = OFF; + +[Resource Reservations] +layer = OFF; + +[Fitter Report Format] + +[Power] + +[Source Constraint Option] + +[Fast Bypass] + +[OSM Bypass] + +[Input Registers] + +[Netlist/Delay Format] +NetList = VHDL; + +[IO Types] +layer = OFF; + +[Pullup] + +[Slewrate] + +[Region] + +[Timing Constraints] + +[HSI Attributes] + +[Input Delay] + +[opt global constraints list] + +[Explorer User Settings] + +[Pin attributes list] + +[global constraints list] + +[Global Constraints Process Update] + +[pin lock limitation] + +[LOCATION ASSIGNMENTS LIST] + +[RESOURCE RESERVATIONS LIST] + +[individual constraints list] + +[Attributes list setting] + +[Timing Analyzer] + +[PLL Assignments] + +[Dual Function Macrocell] + +[Explorer Results] + +[VHDL synplify constraints] + +[VHDL spectrum constraints] + +[verilog synplify constraints] + +[verilog spectrum constraints] + +[VHDL synplify constraints list] + +[VHDL spectrum constraints list] + +[verilog synplify constraints list] + +[verilog spectrum constraints list] + +[Power Guard] + +[ORP Bypass] + +[Register Powerup] diff --git a/sw/cpld_test/cpld_test.naf b/sw/cpld_test/cpld_test.naf new file mode 100644 index 0000000..e69de29 diff --git a/sw/cpld_test/cpld_test.prj b/sw/cpld_test/cpld_test.prj new file mode 100644 index 0000000..eb5548a --- /dev/null +++ b/sw/cpld_test/cpld_test.prj @@ -0,0 +1,34 @@ +#-- Lattice Semiconductor Corporation Ltd. +#-- Synplify OEM project file //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj +#-- Written on Thu Jun 01 13:51:28 2017 + + +#device options +set_option -technology mach +set_option -part M4A5-32 + +#compilation/mapping options + +#map options + +#simulation options +set_option -write_verilog false +set_option -write_vhdl false + +#timing analysis options +set_option -synthesis_onoff_pragma false + +#-- add_file options +add_file -vhdl -lib work "cpld_test.vhd" + +#-- top module name +set_option -top_module cpld_test + +#-- set result format/file last +project -result_file "cpld_test.edi" + +#-- error message log file +project -log_file cpld_test.srf + +#-- run Synplify with 'arrange VHDL file' +project -run diff --git a/sw/cpld_test/cpld_test.rev b/sw/cpld_test/cpld_test.rev new file mode 100644 index 0000000..e8bfb3d --- /dev/null +++ b/sw/cpld_test/cpld_test.rev @@ -0,0 +1,3 @@ + + + diff --git a/sw/cpld_test/cpld_test.srf b/sw/cpld_test/cpld_test.srf new file mode 100644 index 0000000..801fff8 --- /dev/null +++ b/sw/cpld_test/cpld_test.srf @@ -0,0 +1,25 @@ +#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 +#install: C:\ispLEVER_Classic2\synpbase +#OS: Windows 7 6.1 +#Hostname: PC805012 + +#Implementation: cpld_test + +$ Start of Compile +#Thu Jun 01 13:51:51 2017 + +Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 +@N|Running in 32-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +Top entity isn't set yet! +@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration +@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier +2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd +@END +@E|Parse errors encountered - exiting +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Thu Jun 01 13:51:51 2017 + +###########################################################] diff --git a/sw/cpld_test/cpld_test.srr b/sw/cpld_test/cpld_test.srr new file mode 100644 index 0000000..801fff8 --- /dev/null +++ b/sw/cpld_test/cpld_test.srr @@ -0,0 +1,25 @@ +#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 +#install: C:\ispLEVER_Classic2\synpbase +#OS: Windows 7 6.1 +#Hostname: PC805012 + +#Implementation: cpld_test + +$ Start of Compile +#Thu Jun 01 13:51:51 2017 + +Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 +@N|Running in 32-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +Top entity isn't set yet! +@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration +@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier +2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd +@END +@E|Parse errors encountered - exiting +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Thu Jun 01 13:51:51 2017 + +###########################################################] diff --git a/sw/cpld_test/cpld_test.syn b/sw/cpld_test/cpld_test.syn new file mode 100644 index 0000000..06b6554 --- /dev/null +++ b/sw/cpld_test/cpld_test.syn @@ -0,0 +1,11 @@ +JDF B +// Created by Version 2.0 +PROJECT cpld_test +DESIGN cpld_test Normal +DEVKIT M4A5-32/32-10JC +ENTRY Pure VHDL +MODULE cpld_test.vhd +MODSTYLE cpld_test Normal +SYNTHESIS_TOOL Synplify +SIMULATOR_TOOL ActiveHDL +TOPMODULE cpld_test diff --git a/sw/cpld_test/cpld_test.vhd b/sw/cpld_test/cpld_test.vhd new file mode 100644 index 0000000..b1161e9 --- /dev/null +++ b/sw/cpld_test/cpld_test.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity cpld_test is + IN_PIN: in std_logic; + OUT_PIN: out std_logic; +end; + +architecture behavioral of cpld_test is +begin + OUT_PIN <= not(IN_PIN); +end behavioral; + diff --git a/sw/cpld_test/cpld_test_tcl.ini b/sw/cpld_test/cpld_test_tcl.ini new file mode 100644 index 0000000..e69de29 diff --git a/sw/cpld_test/run_options.txt b/sw/cpld_test/run_options.txt new file mode 100644 index 0000000..e4fea81 --- /dev/null +++ b/sw/cpld_test/run_options.txt @@ -0,0 +1,56 @@ +#-- Synopsys, Inc. +#-- Version I-2014.03LC +#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\run_options.txt +#-- Written on Thu Jun 01 13:51:51 2017 + + +#project files +add_file -vhdl -lib work "./cpld_test.vhd" + + + +#implementation: "cpld_test" +impl -add cpld_test -type fpga + +#device options +set_option -technology mach +set_option -part M4A5-32 +set_option -package "" +set_option -speed_grade "" +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "cpld_test" + +# mapper_options +set_option -frequency 1 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice ispMACH4000 +set_option -maxfanin 20 +set_option -RWCheckOnRam 1 +set_option -maxterms 16 +set_option -areadelay 0 +set_option -disable_io_insertion 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "./cpld_test.edi" + +#set log file +set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" +impl -active "cpld_test" diff --git a/sw/cpld_test/scratchproject.prs b/sw/cpld_test/scratchproject.prs new file mode 100644 index 0000000..9db3bb5 --- /dev/null +++ b/sw/cpld_test/scratchproject.prs @@ -0,0 +1,54 @@ +#-- Synopsys, Inc. +#-- Version I-2014.03LC +#-- Project file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\scratchproject.prs + +#project files +add_file -vhdl -lib work "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.vhd" + + + +#implementation: "cpld_test" +impl -add \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test -type fpga + +#device options +set_option -technology mach +set_option -part M4A5-32 +set_option -package "" +set_option -speed_grade "" +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "cpld_test" + +# mapper_options +set_option -frequency 1 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice ispMACH4000 +set_option -maxfanin 20 +set_option -RWCheckOnRam 1 +set_option -maxterms 16 +set_option -areadelay 0 +set_option -disable_io_insertion 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.edi" + +#set log file +set_option log_file "//nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.srf" +impl -active "cpld_test" diff --git a/sw/cpld_test/stdout.log b/sw/cpld_test/stdout.log new file mode 100644 index 0000000..968f5e3 --- /dev/null +++ b/sw/cpld_test/stdout.log @@ -0,0 +1,35 @@ +Running in Lattice mode + + +Starting: C:\ispLEVER_Classic2\synpbase\bin\mbin\synbatch.exe +Install: C:\ispLEVER_Classic2\synpbase +Date: Thu Jun 01 13:51:51 2017 +Version: I-2014.03LC + +Arguments: -product synplify_pro -batch //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test\cpld_test.prj +ProductType: synplify_pro + + + + + +log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" + +Running cpld_test|cpld_test + +Running: Compile on cpld_test|cpld_test + +Running: Compile Process on cpld_test|cpld_test + +Running: Compile Input on cpld_test|cpld_test +compiler exited with errors +Job: "compiler" terminated with error status: 2. +See log file: "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr" +Return Code: 2 +Run Time:0h:00m:00s +Copied \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr to \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srf + +exit status=2 + +exit status=2 + diff --git a/sw/cpld_test/synlog.tcl b/sw/cpld_test/synlog.tcl new file mode 100644 index 0000000..403d18e --- /dev/null +++ b/sw/cpld_test/synlog.tcl @@ -0,0 +1 @@ +project -load //nas001/account_pif/_prossn/samb_3/lab3/projects/z80upc/sw/cpld_test/cpld_test.prj diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt new file mode 100644 index 0000000..fb62f97 --- /dev/null +++ b/sw/cpld_test/synlog/report/cpld_test_compiler_errors.txt @@ -0,0 +1,4 @@ +@E: CD169 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":7:1:7:6|Illegal declaration +@E: CD213 :"\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd":13:1:13:7|Undefined identifier +@E|Parse errors encountered - exiting + diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt b/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt new file mode 100644 index 0000000..6c7370d --- /dev/null +++ b/sw/cpld_test/synlog/report/cpld_test_compiler_notes.txt @@ -0,0 +1,3 @@ +@N|Running in 32-bit mode +@N: CD720 :"C:\ispLEVER_Classic2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns + diff --git a/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml b/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml new file mode 100644 index 0000000..937182a --- /dev/null +++ b/sw/cpld_test/synlog/report/cpld_test_compiler_runstatus.xml @@ -0,0 +1,41 @@ + + + + + + \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr + Start of Compile + + + Failed + + + + 2 + \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_notes.txt + + + 0 + \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_warnings.txt + + + 3 + \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synlog\report\cpld_test_compiler_errors.txt + + + - + + + 0h:00m:00s + + + - + + + 1496317911 + + + \ No newline at end of file diff --git a/sw/cpld_test/syntmp/closed.png b/sw/cpld_test/syntmp/closed.png new file mode 100644 index 0000000..0d78634 Binary files /dev/null and b/sw/cpld_test/syntmp/closed.png differ diff --git a/sw/cpld_test/syntmp/cmdrec_compiler.log b/sw/cpld_test/syntmp/cmdrec_compiler.log new file mode 100644 index 0000000..24cfe61 --- /dev/null +++ b/sw/cpld_test/syntmp/cmdrec_compiler.log @@ -0,0 +1,7 @@ +C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe -osyn \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs -top cpld_test -prodtype synplify_pro -nostructver -dfltencoding sequential -encrypt -pro -dmgen \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd -loga \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr +rc:2 success:0 +\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\synwork\cpld_test_comp.srs|o|0|0 +\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd|i|1496311903|284 +\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.srr|o|1496317911|1349 +C:\ispLEVER_Classic2\synpbase\bin64\c_vhdl.exe|i|1401224104|5533184 +C:\ispLEVER_Classic2\synpbase\bin\c_vhdl.exe|i|1401223898|2046976 diff --git a/sw/cpld_test/syntmp/cpld_test_srr.htm b/sw/cpld_test/syntmp/cpld_test_srr.htm new file mode 100644 index 0000000..a234dd1 --- /dev/null +++ b/sw/cpld_test/syntmp/cpld_test_srr.htm @@ -0,0 +1,29 @@ +
+
+#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
+#install: C:\ispLEVER_Classic2\synpbase
+#OS: Windows 7 6.1
+#Hostname: PC805012
+
+#Implementation: cpld_test
+
+$ Start of Compile
+#Thu Jun 01 13:51:51 2017
+
+Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
+@N: :  | Running in 32-bit mode 
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+Top entity isn't set yet!
+@E:CD169 : cpld_test.vhd(7) | Illegal declaration
+@E:CD213 : cpld_test.vhd(13) | Undefined identifier
+2 errors parsing file \\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd
+@END
+@E: :  | Parse errors encountered - exiting 
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu Jun 01 13:51:51 2017
+
+###########################################################]
+
+
 diff --git a/sw/cpld_test/syntmp/cpld_test_toc.htm b/sw/cpld_test/syntmp/cpld_test_toc.htm new file mode 100644 index 0000000..6e8aa83 --- /dev/null +++ b/sw/cpld_test/syntmp/cpld_test_toc.htm @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/sw/cpld_test/syntmp/open.png b/sw/cpld_test/syntmp/open.png new file mode 100644 index 0000000..a227005 Binary files /dev/null and b/sw/cpld_test/syntmp/open.png differ diff --git a/sw/cpld_test/syntmp/run_option.xml b/sw/cpld_test/syntmp/run_option.xml new file mode 100644 index 0000000..365c522 --- /dev/null +++ b/sw/cpld_test/syntmp/run_option.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + diff --git a/sw/cpld_test/syntmp/statusReport.html b/sw/cpld_test/syntmp/statusReport.html new file mode 100644 index 0000000..1914c86 --- /dev/null +++ b/sw/cpld_test/syntmp/statusReport.html @@ -0,0 +1,49 @@ + + + + Project Status Summary Page + + + + + + +
+ + + + + + + +
Project Settings
Project Name cpld_test Implementation Name cpld_test
Top Module cpld_test Resource Sharing 1
Disable I/O Insertion 0 FSM Compiler 1

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Run Status
Job NameStatusCPU TimeReal TimeMemoryDate/Time
Compile InputError203-0m:00s-01.06.2017
13:51:51
Map & Optimizeout-of-date0m:00s
+
+ \ No newline at end of file diff --git a/sw/cpld_test/synwork/cpld_test_comp.fdeporig b/sw/cpld_test/synwork/cpld_test_comp.fdeporig new file mode 100644 index 0000000..b63dfe0 --- /dev/null +++ b/sw/cpld_test/synwork/cpld_test_comp.fdeporig @@ -0,0 +1,22 @@ +#defaultlanguage:vhdl +#OPTIONS:"|-top|cpld_test|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work" +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\bin\\c_vhdl.exe":1401223898 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\location.map":1310457374 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std.vhd":1401223722 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\std1164.vhd":1401223722 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\numeric.vhd":1401223722 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\arith.vhd":1401223722 +#CUR:"C:\\ispLEVER_Classic2\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722 +#CUR:"\\\\nas001\\account_pif\\_prossn\\samb_3\\lab3\\projects\\z80upc\\sw\\cpld_test\\cpld_test.vhd":1496311903 +0 "\\nas001\account_pif\_prossn\samb_3\lab3\projects\z80upc\sw\cpld_test\cpld_test.vhd" vhdl + +# Dependency Lists (Uses list) +0 -1 + +# Dependency Lists (Users Of) +0 -1 + +# Design Unit to File Association +arch work cpld_test behavioral 0 -- cgit v1.2.1