From 156f243ab58c836ef04d10ded661ecec44f62a8d Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 13 Apr 2017 16:27:19 +0200 Subject: scheme update and PCB start add missing capacitor and resistor values (serial XTAL) create new eurocard standard compliant PCB for the uPC and other minor fixes --- hw/MainBoard.PcbDoc | Bin 0 -> 708096 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 hw/MainBoard.PcbDoc (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc new file mode 100644 index 0000000..d10d84b Binary files /dev/null and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From a952876ae9787d603cf5cf5c19b7f0be34e883f2 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 28 Apr 2017 18:19:42 +0200 Subject: start printed circuit board design wired: - clock circiuts - reset button set layout for: - CPU & memory - serial interface --- hw/MainBoard.PcbDoc | Bin 708096 -> 1265152 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index d10d84b..5f6c233 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 98d8ac2db3f8c0ee75a3edc6e89f68af03c106cf Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 5 May 2017 08:36:43 +0200 Subject: add switches datasheets for footprints --- hw/MainBoard.PcbDoc | Bin 1265152 -> 1287168 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 5f6c233..6560cfd 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 6d90fa4ec93cfb664927ff645743e92cb0582dae Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 5 May 2017 16:27:15 +0200 Subject: complete wiring for serial interface connector and logic other changes: - new layout, probably the board will have to be resized to a nonstandard size (currently 2EUROCARD) - new footprint HDR5x2_SOCKET for standard 5x2 flatcable connectors --- hw/MainBoard.PcbDoc | Bin 1287168 -> 1235456 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 6560cfd..7e6fabf 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 7439592a67e7f63a286dc6527164834329fdc29b Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 9 May 2017 11:21:42 +0200 Subject: created new layout (starting over) the old layout is still under hw/MainBoard1.PcbDoc --- hw/MainBoard.PcbDoc | Bin 1235456 -> 1204224 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 7e6fabf..bc68acd 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 973b4e9b09ed9e36953c4ea351405fdad1d2c9eb Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 18 May 2017 14:19:49 +0200 Subject: wires from DB-9 and HDR5x2 connector to MAX214 (U7) and crystal for TL16C550 --- hw/MainBoard.PcbDoc | Bin 1204224 -> 1227264 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index bc68acd..4588507 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 8992f39ebcbf82fd02b246dcf8f8ed3a69f7b81b Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 18 May 2017 14:44:25 +0200 Subject: wiring for P4 and P5 (I/O ports) and circuits for CLKs and RST --- hw/MainBoard.PcbDoc | Bin 1227264 -> 1233408 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 4588507..dad035f 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 7cf70014c1edf75c7e2b26eba24b0a02ced853f4 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 18 May 2017 15:50:51 +0200 Subject: wiring for CTC (U8) to address bus and data bus --- hw/MainBoard.PcbDoc | Bin 1233408 -> 1259008 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index dad035f..1775dd6 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 28222d73027a1879a5c39e766c1a835e069d1341 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Thu, 18 May 2017 17:10:19 +0200 Subject: new traces for cpu signals and for high address to the MMU / addr decoder there are also many other minor changes to connect various wires --- hw/MainBoard.PcbDoc | Bin 1259008 -> 1277952 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 1775dd6..1909738 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From 3c5918139029f8740c46cab4d946e103bdc29706 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 19 May 2017 09:41:19 +0200 Subject: wiring for 7 segment displays and traces for the remaining CPU signals --- hw/MainBoard.PcbDoc | Bin 1277952 -> 1306624 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 1909738..73260e5 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From f2418d7f5a9734590c4e0d3392886423b2e818a9 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Fri, 19 May 2017 16:14:00 +0200 Subject: finish wiring and add eurocard compliant standard holes since there wasn't enough space (I should have added the holes before beginning) there are only 4 holes instead of 6 (2 will be cut out since the space is unused). --- hw/MainBoard.PcbDoc | Bin 1306624 -> 1333760 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 73260e5..983ffe1 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1 From a29b4fd588d6f3136bfef0d5dc1ee40ead328b15 Mon Sep 17 00:00:00 2001 From: Nao Pross Date: Tue, 23 May 2017 11:51:48 +0200 Subject: board complete, generate gerber (x2) files this is probably the last commit before printing the PCB, unless there are some other errors in the board design --- hw/MainBoard.PcbDoc | Bin 1333760 -> 1329152 bytes 1 file changed, 0 insertions(+), 0 deletions(-) (limited to 'hw/MainBoard.PcbDoc') diff --git a/hw/MainBoard.PcbDoc b/hw/MainBoard.PcbDoc index 983ffe1..026c086 100644 Binary files a/hw/MainBoard.PcbDoc and b/hw/MainBoard.PcbDoc differ -- cgit v1.2.1